x86 Instruction Set – XOP

Introduction

XOP (eXtended Operations) is a set of AMD vector instructions. It came with the Bulldozer processors in 2011, together with FMA4, and grew out of AMD’s SSE5 plans of 2007. Most of it works on integers: multiply-accumulate, horizontal adds, compares with a predicate, a bitwise select, a byte permute, and shifts and rotates whose count can differ in each element. It also has a floating-point fraction instruction and a two-source permute of floats.

A program checks CPUID leaf 80000001H, ECX bit 11 (XOP), and, as for VEX instructions, that the operating system saves the AVX state (CPUID leaf 01H, ECX bit 27, OSXSAVE, and bits 1 and 2 of XCR0). AMD dropped XOP from Zen (2017) on: those processors do not report it in CPUID, and programs must not use it there. No Intel processor has it.

The instructions use the xmm registers: 16 in 64-bit mode, 8 elsewhere. Only vpcmov, vfrczps, vfrczpd and the two vpermil2 instructions have 256-bit forms on the ymm registers. A 128-bit form clears bits 255:128 of its destination, as VEX instructions do.

The XOP prefix

XOP instructions start with the byte 8F, then two bytes laid out as the three-byte VEX prefix (C4) lays them out:

• byte 1: R, X and B, inverted, then five bits of map number: 8, 9 or 10 (written 08, 09 and 0A below);
• byte 2: W, then vvvv (a register, inverted), then L (0 for 128 bits, 1 for 256), then pp, which must be 00.

Then come the opcode, the ModRM byte and the rest, as in any instruction. 8F is also pop r/m, which needs ModRM.reg = 0. Bits 5:3 of the byte after 8F hold B and the top two bits of the map number, and a map number of 8 or more always sets one of those, so the two cannot be confused.

The maps hold:

• map 08: instructions with an immediate byte. In the four-operand instructions the fourth register is in imm8[7:4] (written /is4);
• map 09: instructions with no immediate, and also the TBM and LWP instructions on the general registers (see Bit manipulation and System instructions);
• map 0A: instructions with a 32-bit immediate, which are TBM’s bextr and LWP’s lwpins and lwpval.

The encodings below are written as XOP.L.map.W opcode, in the style of Intel’s VEX notation. AMD’s manual writes the same thing as the prefix bits: XOP.128.08.W0 A2 /r /is4 is AMD’s 8F RXB.08 0.src.0.00 A2 /r is4.

VEX.W (here XOP.W) does two jobs. In the four-operand instructions and the shifts and rotates by a register, it swaps the last two sources, so that either can be in memory. Everywhere else it must be 0.

Instructions

Notes

• VPERMIL2PS and VPERMIL2PD. These two are not XOP-encoded: they use a VEX prefix, in map 0F 3A with 66, beside FMA4. AMD documents them with XOP, and the XOP CPUID bit reports them. The last operand is the low four bits of the /is4 byte; the top four name the fourth register. We show those four bits as the fifth operand, as LLVM does.
• Lengths and W. Every XOP instruction here takes XOP.pp = 00. Apart from vpcmov and the vfrcz packed forms, XOP.L must be 0. XOP.W must be 0 except where the tables show a W1 form.
• No prefixes. A 66, F2, F3, LOCK or REX prefix before 8F makes the instruction invalid (#UD), as before VEX. We show it as invalid, as a processor runs it; LLVM does not.
• Every mode. We decode XOP in 16-bit and 32-bit code as well as in 64-bit code. Since a map number of 8 or more cannot be a pop, there is no doubt about the byte 8F in any mode.
• The fourth register outside 64-bit mode. Only xmm0–xmm7 exist there, so bit 7 of the /is4 byte has no register to name. We ignore it, as GNU binutils does; LLVM does not.
• Exceptions. The integer instructions raise no floating-point exceptions and do not change EFLAGS. vfrcz raises the SIMD floating-point exceptions through MXCSR. A memory operand need not be aligned.
• Assembler names. GNU and LLVM use AMD’s mnemonics. Compilers reach the instructions through intrinsics in xopintrin.h, such as _mm_perm_epi8 for vpperm and _mm_cmov_si128 for vpcmov.

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