x86 Instruction Set – 3DNow!

Introduction

3DNow! came with AMD’s K6-2 in 1998, a year before Intel’s SSE. It does arithmetic on two single-precision (32-bit) floating-point numbers at once, held in the eight 64-bit MMX registers, mm0 to mm7. It was meant for the geometry stage of 3D games. The Athlon added five more instructions in 1999 (AMD calls them the 3DNow! extensions; they are often called Extended 3DNow!), together with integer instructions on MMX registers that match those of SSE. The IDT WinChip 2 and VIA’s early C3 processors also carried 3DNow!. Intel never did.

Because the MMX registers are the x87 registers underneath, a program ends a block of 3DNow! code with femms (or emms) before it uses the x87 unit again.

A program checks for 3DNow! with CPUID leaf 8000_0001h: EDX bit 31, and for the extensions with EDX bit 30.

Dropped. In August 2010 AMD said it would remove 3DNow! from its processors, apart from prefetch and prefetchw. The Bulldozer family (family 15h, 2011) and every AMD processor since lack it: CPUID clears both bits, and the 0F 0F instructions raise #UD. The two prefetches are still there, with a CPUID bit of their own; they are on the cache and memory ordering page.

Encoding

All but femms share one opcode, 0F 0F. The byte that says which instruction it is comes last, after the ModRM byte and any SIB byte and displacement, where an immediate would be:

0F 0F /r ib     pfadd mm1, mm2/m64     0F 0F C1 9E   pfadd mm0, mm1

Every one takes an MMX register in ModRM.reg as its destination and first source, and an MMX register or a 64-bit memory operand in ModRM.r/m as its second source. REX.W, REX.R and REX.B have no effect on them. In the tables the final byte is shown after /r.

The instructions

The two values in a register are called low (bits 31:0) and high (bits 63:32).

Notes

• Floating point. The 3DNow! instructions raise no floating-point exceptions and use neither MXCSR nor the x87 control word. They do not follow IEEE 754 in full; AMD’s manual gives how each one treats zeros, denormals, infinities and overflow.
• Prefixes. AMD gives F2 and F3 no meaning on 0F 0F. The disassembler, as LLVM does, takes them as part of the instruction and leaves them out of the text.
• Unknown suffixes. A final byte that is none of the 24 above is shown as an invalid instruction. AMD’s Geode LX added two more, pfrcpv (86) and pfrsqrtv (87); the disassembler does not decode them.
• The MMX extensions. The integer instructions the Athlon added on MMX registers (pavgb, pshufw, pminub and the rest) are the same instructions as in SSE, and are on the SSE page.

Links