x86 Instruction Set – AVX-512 FP16

Introduction

AVX-512 FP16 does arithmetic on half-precision numbers: IEEE 754 binary16, with a sign bit, 5 exponent bits and 10 fraction bits. Before it, x86 could only convert halves to and from single precision (F16C, and the same conversions in AVX-512 Foundation). FP16 adds the whole set of floating-point operations for them: add, subtract, multiply, divide, square root, minimum and maximum, fused multiply-add, compares, the AVX-512 helpers (VGETEXP, VGETMANT, VREDUCE, VRNDSCALE, VSCALEF, VFPCLASS), conversions to and from every integer and floating-point type, and multiplies of complex numbers.

The instructions use the AVX-512 state. A packed instruction works on 8, 16 or 32 halves in an xmm, ymm or zmm register (xmm0 to xmm31 and so on); a scalar one (the sh forms) works on the low word of an xmm register and copies the rest of the first source. The mask registers k1 to k7 select which elements are written, with merging or zeroing ({z}). The rounding mode comes from MXCSR, or from the instruction itself ({er}) on the 512-bit and scalar register forms.

Intel brought FP16 with the Xeon processors code-named Sapphire Rapids (January 2023). It is also part of AVX10.1, so every AVX10 processor has it. A program checks CPUID.(EAX=07H, ECX=0):EDX[bit 23] (AVX512-FP16), and for the 128-bit and 256-bit forms also AVX512VL, CPUID.(EAX=07H, ECX=0):EBX[bit 31].

Most of the instructions sit in two EVEX opcode maps that FP16 added: map 5 holds the half-precision forms of the 0F map’s floating-point instructions, at the same opcodes, and map 6 those of the 0F 38 map. The ones that take an immediate are in the 0F 3A map, with no prefix, beside their ps and pd forms. AVX10.2 later put its BF16 instructions at the same opcodes with other prefixes.

When the explorer disassembles a program, each instruction it shows links to its row on these pages.

Instructions

Packed forms are shown at 512 bits. Each also has a 128-bit and a 256-bit form (EVEX.128 and EVEX.256, with xmm and ymm registers and m128 and m256 memory), without {er} or {sae}. Scalar forms (EVEX.LLIG) ignore the vector length. m16bcst is a single half in memory broadcast to every element.

Notes

• Element size. The tuple types count in 16-bit elements, so an 8-bit displacement is scaled by the vector size for full-vector forms and by 2 for the scalar ones (disp8×N), and broadcast reads one half. The complex multiplies work on dwords: they broadcast a dword, and their scalar forms scale by 4.
• Complex destinations. In VFMULCPH, VFCMULCPH, VFMADDCPH, VFCMADDCPH and their scalar forms the destination must not be the same register as either source; if it is, the processor raises #UD.
• Exceptions. The arithmetic raises the usual SIMD floating-point exceptions through MXCSR. {sae} suppresses them on the register forms that take it. The complex multiplies run as if every MXCSR exception were masked.
• Vector length. {er} and {sae} exist only on the 512-bit and scalar register forms: EVEX.b on a register form turns L′L into the rounding mode.
• VMOVW and W. Intel marks VMOVW’s general-register forms WIG (W is ignored). We show W = 1 on the register form as a 64-bit register, as LLVM does; the word moved is the same.
• Compare immediates. An immediate of 0 to 31 is shown by its predicate name (vcmpltph and so on); a larger one, whose top bits are ignored, is shown as vcmpph with the immediate.

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