x86 Instruction Set – AVX-512 Foundation

Introduction

AVX-512 widens the vector registers to 512 bits, doubles their number to 32, and adds eight mask registers that let almost every instruction work on only some of its elements. Its instructions are written with a new prefix, EVEX. The Foundation set, AVX-512 F, holds the core: the floating-point and 32-bit and 64-bit integer operations, loads and stores, shuffles, conversions, gathers and scatters. Every processor with AVX-512 has it. The other sets build on it: the mask register instructions, BW, DQ and CD, the later extensions and FP16.

The sections below explain the parts of AVX-512 that every one of those pages uses.

The registers

• zmm0 to zmm31 are 512 bits wide. The low 256 bits of each are a ymm register and the low 128 bits an xmm register, so ymm16 to ymm31 and xmm16 to xmm31 are new as well; only EVEX instructions can name them. Outside 64-bit mode only zmm0 to zmm7 can be named.
• An EVEX or VEX instruction that writes an xmm or ymm register clears the rest of its zmm register, up to bit 511.
• k0 to k7 are the opmask registers, 64 bits each. Bit i of a mask belongs to element i of a vector. They are described, with the instructions that work on them, on the mask registers page.
• The state is saved by XSAVE as three components: 5 (k0 to k7), 6 (the upper 256 bits of zmm0 to zmm15) and 7 (zmm16 to zmm31).

The EVEX prefix

EVEX is four bytes: 62 and three payload bytes, then the opcode, the ModRM byte and the rest, as in any instruction. Outside 64-bit mode, 62 is BOUND; it is read as EVEX when the next byte’s top two bits are 11, which as a ModRM byte would be a register operand that BOUND cannot take. The full layout is on the instruction encoding page. In short:

In Intel’s notation an EVEX encoding is written like EVEX.512.66.0F38.W0 58 /r: the vector length, the implied prefix, the map, the W bit, the opcode and how ModRM is used. LLIG means the length is ignored (scalars) and WIG that W is ignored.

Masking and zeroing

• EVEX.aaa names the mask, k1 to k7, written {k1} after the destination. 000 means no mask: every element is written. So k0 cannot be a write mask.
• An element whose mask bit is 0 is not computed. It raises no floating-point exception, and a memory fault in it is suppressed.
• Merging (EVEX.z = 0) leaves such an element of the destination as it was. Zeroing (EVEX.z = 1), written {z}, clears it.
• A store to memory can only merge: the masked-off elements of memory are not written, and {z} is not allowed.
• A compare writes a mask, and its {k2} is ANDed into the result: bits whose k2 bit is 0 are cleared.
• Gathers and scatters must have a mask other than k0, and clear its bits as the elements are done.

Embedded broadcast

On an instruction whose last source may be in memory, EVEX.b = 1 with a memory operand reads one element and repeats it across the vector. Intel writes the operand as m32bcst or m64bcst; LLVM shows it as dword ptr [rax]{1to16}. A zmm register holds 16 dwords or 8 qwords, so the forms are {1to16} and {1to8}, and {1to4} or {1to2} with AVX512VL. Only instructions of the full and half tuple types (below) can broadcast, on 32-bit or 64-bit elements.

Embedded rounding and {sae}

With EVEX.b = 1 and a register (not memory) last operand, EVEX.L′L gives a rounding mode for this one instruction instead of a length, and the length is 512 bits (or ignored, for a scalar):

Embedded rounding also suppresses all floating-point exceptions (“sae”): no exception is raised and no MXCSR flag is set. Instructions that do not round (compares, minimum and maximum, conversions to a wider type) take {sae} alone with the same EVEX.b bit. Intel marks the forms that allow them with {er} and {sae}.

disp8×N and the tuple types

With EVEX, an 8-bit displacement is multiplied by N, the size of the memory operand the instruction touches, so a short displacement reaches 128 elements either side. For example vaddps zmm0, zmm1, [rax+0x40] is encoded with disp8 = 1. Each instruction has a tuple type that sets N. A 32-bit displacement is never scaled.

The tables below give each form’s tuple type after its encoding.

Vector lengths and AVX512VL

EVEX.L′L picks the length: 00 for 128 bits (xmm), 01 for 256 (ymm) and 10 for 512 (zmm). 11 is reserved. AVX-512 F by itself has only the 512-bit forms and the scalar ones. AVX512VL, from Skylake-SP (2017) on, adds the 128-bit and 256-bit forms of the same instructions (written EVEX.128 and EVEX.256), which work on xmm and ymm registers, with masks and on all 32 registers.

The tables give the 512-bit form. Unless a row says otherwise, each packed instruction also has its 128-bit and 256-bit forms with AVX512VL: replace zmm with xmm or ymm, m512 with m128 or m256, and EVEX.512 with EVEX.128 or EVEX.256; a half or quarter operand shrinks in step. Xeon Phi processors have no AVX512VL.

Checking for AVX-512

• CPUID leaf 7, sub-leaf 0: EBX bit 16 is AVX-512 F, and bit 31 is AVX512VL. The other sets have bits of their own, given on their pages.
• The operating system must have enabled the state: CPUID leaf 1 ECX bit 27 (OSXSAVE) is set, and XGETBV with ECX = 0 returns XCR0 with bits 1, 2, 5, 6 and 7 set.

Processors

• Intel announced AVX-512 in July 2013. It first shipped in the Xeon Phi x200, Knights Landing, in 2016, with F, CD, ER and PF; then in the Skylake-SP Xeons and Skylake-X Core i9s in 2017, with F, CD, BW, DQ and VL. Later Xeons kept it and added sets.
• Intel’s client processors with AVX-512, besides the Skylake-X Core i9s, were Cannon Lake (2018), Ice Lake (2019), Tiger Lake (2020) and Rocket Lake (2021).
• Alder Lake (late 2021) mixes performance cores, which have the AVX-512 hardware, with efficiency cores, which do not. Intel never supported AVX-512 on it. Early firmware let it run with the efficiency cores turned off; Intel blocked that in firmware and microcode early in 2022 and then began fusing it off in the silicon. Intel’s hybrid client chips since then (Raptor Lake, Meteor Lake, Lunar Lake, Arrow Lake) have no AVX-512.
• AMD added AVX-512 with Zen 4 (2022), and Zen 5 (2024) has it too.
• In July 2023 Intel announced AVX10, which gathers AVX-512 into versions that every core of a processor supports. The first AVX10 specification let a processor stop at 256 bits; the March 2025 revision made 512-bit vectors part of every AVX10 processor again.

Dropping a program on any page of this site opens it in the explorer, which decodes its code, AVX-512 included, and links each instruction to its row here.

The instructions

Every instruction on this page is AVX-512 F, which came with Intel’s Xeon Phi Knights Landing (2016) and the Skylake-SP Xeons (2017). The 128-bit and 256-bit forms also need AVX512VL. In the Forms column, {k1}{z} marks a destination that takes a mask and zeroing, {k1} one that takes a mask only.

Moves

Broadcast, insert and extract

Floating-point arithmetic

ps works on 16 singles, pd on 8 doubles, ss and sd on the lowest element only (the rest of the destination comes from the first source).

Fused multiply-add

The EVEX forms of the FMA3 instructions, with masks, broadcast and embedded rounding. Each rounds once. Calling the operands a, b and c in order, the number names which are multiplied and which is added: 132 is a·c + b, 213 is b·a + c and 231 is b·c + a; the result goes to a. fmsub subtracts instead, fnmadd negates the product, fnmsub does both. fmaddsub subtracts in the even elements and adds in the odd ones, and fmsubadd the other way round.

Floating-point compares

VCMPPS and its kin compare by the predicate in imm8 bits 4–0 and write one mask bit per element. The disassembler shows an imm8 of 0 to 31 as the predicate’s name, as Intel’s manual and LLVM do (vcmplt_oqps k1, zmm2, zmm3), and leaves the immediate out; a larger imm8 is shown as a number. Ordered predicates are false if either value is a NaN, unordered ones true. Signalling ones raise the invalid exception for a quiet NaN too; non-signalling ones only for a signalling NaN.

Conversions

A conversion to an integer rounds as MXCSR (or {er}) says; the ones with a t, for truncate, round towards zero. A value that does not fit gives the “integer indefinite” value: 80000000h (signed) or FFFFFFFFh (unsigned), and the 64-bit equivalents. The unsigned conversions (udq, usi) are new in AVX-512.

Integer arithmetic

Logic

AVX-512 F has the bitwise operations on integers only, by dword or qword (which matters for the mask and for broadcast). The floating-point forms, VANDPS and the rest, came with AVX-512 DQ.

Shifts and rotates

The immediate shifts and rotates take their destination from EVEX.vvvv and their source from ModRM.rm, which may be memory; ModRM.reg is part of the opcode. A shift count at or above the element size gives 0, or all sign bits for an arithmetic shift.

Integer compares and tests

These write a mask, one bit per element. VPCMPD and its kin take the predicate in imm8 bits 2–0: 0 eq, 1 lt, 2 le, 3 false, 4 neq, 5 nlt (not less: greater or equal), 6 nle (greater), 7 true. The disassembler shows predicates 0, 1, 2, 4, 5 and 6 by name, as Intel’s manual and LLVM do, and keeps the immediate for the others.

Shuffles, permutes and unpacks

Blend, compress and expand

Narrowing and widening moves

The narrowing moves (VPMOVDB and the rest) store to their ModRM.rm operand, register or memory; a store to memory takes {k1} but not {z}. Plain ones truncate, s ones saturate as signed, us ones as unsigned.

Gathers and scatters

These address memory with a vector of indices, VSIB: the SIB byte’s index field names a vector register, and each element’s address is base + index × scale + displacement. vm32z is a zmm of dword indices, vm32y a ymm of them, vm64z a zmm of qword indices. The mask, which must not be k0, says which elements to move; each bit is cleared as its element is done, so a gather or scatter interrupted by a fault can be restarted. The gathers take no {z}. Using the same register as destination and index is #UD. The memory operand counts as one element for disp8×N (T1S).

Notes

• Alignment. Only VMOVAPS, VMOVAPD, VMOVDQA32, VMOVDQA64 and the non-temporal moves need aligned memory, to the size of the operand. Every other instruction accepts any address.
• Flags. Only VCOMISS, VCOMISD, VUCOMISS and VUCOMISD change RFLAGS.
• Reserved length. EVEX.L′L = 11 is reserved, except where it holds a rounding mode or the instruction ignores the length. LLVM decodes it as 512 bits; our decoder shows it as an invalid instruction.
• W1 outside 64-bit mode. Intel’s manual gives the W1 forms VMOVDQA64, VMOVDQU64, VINSERTF64X4, VEXTRACTF64X4, VBROADCASTF64X4, VSHUFF64X2 and their integer partners as valid in every mode. LLVM 21 shows them outside 64-bit mode as the W0 instructions (VMOVDQA32 …); our decoder follows Intel.
• General registers outside 64-bit mode. Where W picks a 64-bit general register (VMOVQ at 6E and 7E, VPBROADCASTQ at 7C, VCVTSI2SD and the like), W is ignored outside 64-bit mode and the instruction acts as its 32-bit form, as Intel’s manual says. Our decoder shows that form; for VPBROADCASTQ, LLVM 21 shows a 64-bit register that does not exist there.
• 66 0F 5B with W1 is not an instruction (VCVTPS2DQ is W0, and VCVTQQ2PS is the no-prefix form). LLVM 21 shows it as VCVTQQ2PS; we show it as invalid.
• Each of these differences is a known rule of our tests, which otherwise match LLVM’s output for every instruction on this page in every mode.

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