x86 Instruction Set – AMX

Introduction

AMX (Intel Advanced Matrix Extensions) multiplies small matrices held in tiles: eight new registers, tmm0 to tmm7, each up to 16 rows of 64 bytes (1 KiB). A program first describes the shape of each tile in a 64-byte block, TILECFG, and loads it with LDTILECFG. It then loads tiles from memory, multiplies them with the dot-product instructions (Intel calls this unit TMUL), which add into an accumulator tile, and stores the result. TILERELEASE puts the tiles back in their initial, unconfigured state.

AMX works in 64-bit mode only. Its state is two XSAVE components: 17, XTILECFG (the 64 bytes of TILECFG), and 18, XTILEDATA (the 8 KiB of tile data). The operating system must enable both in XCR0. On Linux, a program must also ask for the tile data with arch_prctl(ARCH_REQ_XCOMP_PERM, XFEATURE_XTILEDATA) before its first AMX instruction. CPUID leaf 1DH describes the palettes (the tile shapes a processor supports) and leaf 1EH the TMUL unit.

Intel first described AMX in 2020, and brought it with the Xeon processors code-named Sapphire Rapids (January 2023). Each later extension has its own CPUID bit:

Withdrawn and announced. Intel announced AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512 and AMX-MOVRS in its Architecture Instruction Set Extensions reference in October 2024. It removed AMX-TRANSPOSE from revision 059 of that reference (September 2025), and AMX-TF32 from the June 2026 revision (062). Diamond Rapids, for which the others were announced, was not on sale when this page was written (November 2026); Intel has given 2027. LLVM 21 still decodes AMX-TRANSPOSE, and so does our disassembler, so its instructions are listed here.

When the explorer disassembles a program, each instruction it shows links to its row on these pages.

TILECFG

LDTILECFG reads, and STTILECFG writes, this 64-byte block. With palette 1, the only one defined so far, tiles 0 to 7 are used and the entries for 8 to 15 must be zero. A reserved byte that is not zero, a palette the processor lacks, or a shape larger than the palette allows makes LDTILECFG raise #GP.

Instructions

Every AMX instruction is VEX.128 with W0, apart from AMX-AVX512’s, which are EVEX.512. The forms marked APX are the same instructions in EVEX form, which APX added so that the address registers can be r16 to r31 (see the APX page). In the dot products, tmm1 is the accumulator (ModRM.reg), tmm2 the first source (ModRM.rm) and tmm3 the second (VEX.vvvv).

Notes

• 64-bit mode only. Outside it the opcodes are invalid.
• Eight tiles. A tile number needs only the three bits of ModRM.reg, ModRM.rm or VEX.vvvv. We treat an encoding whose extra register bits (VEX.R, VEX.B, the top bit of vvvv, and in EVEX form R4, X and B4) would name tile 8 or above as invalid, as LLVM does.
• Tile memory. A load or store without a SIB byte is invalid. A SIB index of 100 (no index register) is shown with no index, as LLVM shows it.
• Unconfigured tiles. The tile instructions other than LDTILECFG, STTILECFG and TILERELEASE raise #UD while the tiles are in the initial state (palette 0).
• AMX-TRANSPOSE’s pair loads name a pair of tiles by its even register; LLVM shows it as that one tile, and so do we.

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