x86 Instruction Set – AVX2 and the later VEX extensions

Introduction

AVX made the vector registers 256 bits wide, but only for floating point: its integer instructions stayed at 128 bits. AVX2 gives almost every integer instruction of SSE2 to SSE4.2 a 256-bit form on the ymm registers. It also adds broadcasts from a register, permutes that cross the two 128-bit halves, shifts with a count per element, masked integer loads and stores, and gathers, which load each element from its own address. Intel brought AVX2 with Haswell, in 2013; AMD added it with Excavator, in 2015. A program checks CPUID leaf 07H, sub-leaf 0, EBX bit 5 (AVX2).

The later extensions on this page are VEX-encoded too. Some are the VEX forms of AVX-512 instructions, for processors without AVX-512; others are new:

• AVX-VNNI (Intel Alder Lake, 2021): the dot products of AVX-512 VNNI, for neural-network inference. CPUID leaf 07H, sub-leaf 1, EAX bit 4.
• AVX-IFMA (Intel Sierra Forest and Lunar Lake, 2024): the 52-bit integer multiply-adds of AVX-512 IFMA, for big-number arithmetic. EAX bit 23 of the same leaf.
• AVX-NE-CONVERT (Intel Sierra Forest and Lunar Lake, 2024): loads of BF16 and FP16 values converted to single precision, and single precision to BF16. EDX bit 5.
• AVX-VNNI-INT8 (Intel Sierra Forest and Lunar Lake, 2024): byte dot products with every mix of signed and unsigned. EDX bit 4.
• AVX-VNNI-INT16 (Intel Arrow Lake and Lunar Lake, 2024): the same for words. EDX bit 10.

Every VEX instruction also needs the operating system to save the AVX state: CPUID leaf 01H, ECX bit 27 (OSXSAVE) must be set, and XGETBV with ECX = 0 must show bits 1 and 2 of XCR0 set. The ymm registers are 16 in 64-bit mode and 8 elsewhere. A 128-bit form clears bits 255:128 of its destination.

Most 256-bit integer instructions work on each 128-bit half (lane) of the register on its own, as two 128-bit instructions would: the unpacks, packs, shuffles, vpalignr, the horizontal adds, the byte shifts and vpsadbw. Only the permutes, broadcasts, inserts and extracts move data between the lanes.

The encodings are written as Intel writes them: VEX.L.pp.map.W opcode, where a missing pp means no prefix (00), WIG means W is ignored, and LIG means L is ignored. See Instruction encoding for the VEX prefix itself.

New AVX2 instructions

256-bit forms of the SSE integer instructions

Each of these is the VEX.256 form of an SSE2, SSSE3 or SSE4 instruction. Its VEX.128 form came earlier, with AVX, and has its row on the AVX page, which each row links to. The legacy SSE forms are on the SSE2, SSE3 and SSSE3 and SSE4 pages. Where an instruction has a source and a destination of different widths, the forms say so.

Later VEX extensions

The dot-product instructions below accumulate into the destination: a is the destination and the accumulator, b and c the second and third operands. AVX-VNNI’s four instructions and AVX-IFMA’s two have EVEX forms with the same names (AVX-512 VNNI and AVX-512 IFMA, on the Later AVX-512 page). Assemblers pick the EVEX form unless told otherwise, so in source code the VEX form is written with a {vex} prefix, as in {vex} vpdpbusd ymm0, ymm1, ymm2. We show the plain mnemonic.

Notes

• Alignment. VEX memory operands need no alignment, except where a row says so (vmovntdqa). The masked moves and gathers cause no fault for an element they do not access.
• Flags. None of these instructions changes EFLAGS.
• VEX.L. The rows show which lengths exist. vpermd, vpermps, vpermq, vpermpd, vperm2i128, vinserti128, vextracti128, vbroadcasti128 and the register form of vbroadcastsd have only VEX.256; with L = 0 they are invalid.
• VEX.W. WIG means VEX.W is ignored. Where W0 or W1 is given, the other value is a different instruction (vpsllvd and vpsllvq) or invalid.
• 16-bit code. VEX instructions run in 16-bit protected mode, so we decode them in 16-bit code too. They are not available in real mode or virtual-8086 mode, where C4 and C5 are les and lds.
• The fourth register outside 64-bit mode. For vpblendvb only xmm0–xmm7 exist there, so bit 7 of the /is4 byte has no register to name. We ignore it, as GNU binutils does; LLVM does not.

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