x86 Instruction Set – AVX10

AVX10.1

AVX10.1 has no instructions of its own. It is the AVX-512 of the Xeon processors code-named Sapphire Rapids, AVX-512 FP16 among it, under the new name. Its instructions are on the AVX-512 pages: Foundation, mask registers, BW, DQ and CD, the later extensions and FP16. The first processors with it were Intel’s Xeon 6 processors with P-cores (Granite Rapids), from 2024. A processor with AVX10.1 still sets the old AVX-512 CPUID bits.

The first versions of the specification let a processor support AVX10 with 256-bit vectors only, and named versions by length (AVX10.1/256, AVX10.1/512); CPUID leaf 24H said which lengths there were. In March 2025, with revision 3.0 of the AVX10 specification, Intel dropped that: every AVX10 processor has 512-bit vectors, and the length bits went away.

AVX10.2

AVX10.2 adds new instructions, all in the tables below: arithmetic on BF16 numbers, IEEE 754-2019 minimum and maximum, compares that set the flags in a new way, conversions to and from 8-bit floating point, saturating conversions to integers, EVEX forms of the AVX-VNNI-INT8 and AVX-VNNI-INT16 dot products, and a few moves. Intel first published its specification in July 2024, and has announced it for the processors code-named Diamond Rapids (Xeon) and Nova Lake (Core). Neither was on sale when this page was written, in November 2026: Intel has given 2027 for Diamond Rapids.

The specification first also gave 256-bit instructions embedded rounding and {sae}, using EVEX’s U bit (bit 2 of its second payload byte), for processors that would have only 256-bit vectors. When 512-bit vectors became compulsory, in March 2025, Intel withdrew it; GNU binutils and LLVM removed it the same month. No processor has it.

The VMOVRS loads (AVX10.2 with MOVRS) are on the cache and memory ordering page.

BF16 arithmetic

BF16 (bfloat16) is the top half of a single-precision number: a sign bit, 8 exponent bits and 7 fraction bits. These instructions are the BF16 forms of the FP16 ones, at the same opcodes with another prefix. They take no rounding or {sae} operand.

Minimum and maximum (IEEE 754-2019)

VMINMAX does one of the minimum and maximum operations of IEEE 754-2019, which imm8 selects: minimum and maximum (−0 is less than +0, and a NaN input gives a NaN), their magnitude forms (which compare absolute values), and their “number” forms (which return the number when only one input is a NaN). imm8 also says how the sign of the result is set.

Compares that set the flags

These compare like COMISS and UCOMISS, but also set OF and SF, so that an unordered result never looks like “equal” or “less than”, and each relation can be tested with one condition: the unsigned conditions for greater than, the signed ones for less than. The comx forms signal invalid for any NaN, the ucomx forms only for a signalling NaN.

8-bit floating point

Two 8-bit formats: bf8 is E5M2 (5 exponent bits, 2 fraction bits) and hf8 is E4M3 (4 exponent bits, 3 fraction bits). The conversions from halves round to nearest; the s forms saturate, turning a value too large for the format into its largest finite value. The 2ph forms convert two sources into one full vector; the bias forms add an 8-bit bias, taken from the other source, to each half before converting.

Saturating conversions to 8-bit integers

Each result is an 8-bit integer, saturated to −128…127 (ibs) or 0…255 (iubs) and kept in its own element: a word for the ph and bf16 forms, a dword for the ps forms. The cvtt forms truncate.

Saturating truncations to dwords and qwords

These truncate like VCVTTPS2DQ and the rest, but a result out of range gives the largest or smallest integer of the type instead of the integer indefinite value.

Dot products and sums of differences

The integer dot products are the EVEX forms of AVX-VNNI-INT8 and AVX-VNNI-INT16, with masking, broadcast and the 32 registers. Each multiplies groups of four bytes (or pairs of words) of the two sources and adds the sums to the dwords of the destination. The letters say which source is signed: ss both, su the first, us the second, uu neither; a final s saturates the sum.

Moves

Reference

• Intel 64 and IA-32 Architectures Software Developer’s Manuals – Intel’s manual, which now includes AVX10.1, with links to the AVX10 technical paper and the AVX10.2 specification
• Intel AVX10.2 Architecture Specification – the extension’s own specification
• The Converged Vector ISA: Intel Advanced Vector Extensions 10 – Intel’s technical paper that introduced AVX10 (2023)
• AMD64 Architecture Programmer’s Manual, Volume 4 – AMD’s reference to the 128-bit, 256-bit and 512-bit media instructions