x86 Instruction Set – SSE3 and SSSE3

Introduction

Two small extensions to SSE2 share this page. Both use the XMM registers and MXCSR, as SSE does.

• SSE3 came with the Pentium 4 core called Prescott, in 2004. It adds floating-point instructions that work across a register (horizontal addition, alternating addition and subtraction), moves that duplicate elements, and lddqu. The same extension brought monitor and mwait, and the x87 instruction fisttp, which are described on their own pages. A program checks for SSE3 with CPUID leaf 1: ECX bit 0.
• SSSE3 (Supplemental SSE3) came with the Core 2 in 2006. It adds sixteen integer instructions, among them pshufb, the byte shuffle, and palignr. Each has a form on the 64-bit MMX registers with no prefix and a 128-bit form on the XMM registers with a 66 prefix; both forms are SSSE3. They live in the three-byte opcode maps 0F 38 and 0F 3A. A program checks for SSSE3 with CPUID leaf 1: ECX bit 9.

The 128-bit forms have VEX forms, which came with AVX; their names start with v and they are described on the AVX page. Each row below links to it.

The instructions

In the forms, xmm1 is the ModRM.reg operand and xmm2/m128 the ModRM.r/m operand. NP means that no 66, F2 or F3 prefix may be present.

Notes

• Alignment. In the legacy encodings a 128-bit memory operand must be 16-byte aligned, or the instruction raises #GP; lddqu and movddup’s 64-bit operand are the exceptions. The 64-bit MMX forms have no alignment rule.
• MMX state. The MMX forms of SSSE3 use the x87 register stack as the other MMX instructions do: a program must run emms before x87 code.
• Exceptions. The SSE3 floating-point instructions set the exception flags in MXCSR, as SSE’s do. The SSSE3 instructions are integer instructions and raise no floating-point exceptions.
• Decoding. SSSE3 forms take no F2 or F3 prefix. With one, Intel’s manual calls the encoding reserved; LLVM, and so the disassembler, decodes the instruction as if the prefix were not there.

Links