x86 Instruction Set – Bit manipulation (BMI, ABM, TBM, ADX)

Introduction

These extensions add bit operations on the general registers that would otherwise take several instructions: counting bits, isolating the lowest set bit, extracting a field, gathering or scattering bits by a mask, and shifts and multiplies that leave the flags alone. All of them work on 32-bit or 64-bit operands; POPCNT, LZCNT and TZCNT also on 16-bit ones. Each set has its own CPUID bit:

AMD’s ABM (advanced bit manipulation) was LZCNT and POPCNT together. BMI1 and BMI2 are encoded with a VEX prefix, though they work on general registers, and TBM with AMD’s XOP prefix. Intel’s APX gives most of them EVEX forms in 64-bit mode, which can use R16 to R31, and in which those that set flags may leave them alone ({nf}). The older bit instructions (BT, BSF, BSR, the shifts) are on the Logic, shifts and bits page.

The instructions

In the forms, r32a is the register in ModRM.reg, r32b the register in VEX.vvvv, and r/m32 ModRM.r/m; the 64-bit forms take W1, in 64-bit mode only. In the encodings, VEX.LZ means VEX.L = 0. The TBM encodings are written as AMD’s manual writes them: the XOP prefix 8F, then R, X, B and the map, then W, vvvv (dest where it names the destination), L and pp.

Notes

• APX forms. ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, SARX, SHLX and SHRX have EVEX forms in map 2 and RORX in map 3, at the same opcodes as their VEX forms. ANDN, BEXTR, BLSI, BLSMSK, BLSR and BZHI take NF there. LLVM shows them without {evex}. See APX’s EVEX fields.
• VEX.L must be 0. With L = 1 the disassembler shows the bytes as invalid, as LLVM does.
• Outside 64-bit mode VEX.W is ignored here and the operand size is 32 bits.

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