x86 Instruction Set – AVX-512 BW, DQ and CD

Introduction

Three sets that complete AVX-512 Foundation. They use the same zmm and mask registers and the same EVEX encoding, masking, broadcast, rounding and disp8×N, all explained on the AVX-512 Foundation page; the tuple type after each encoding below is defined there too.

• AVX-512 BW (byte and word) gives the 8-bit and 16-bit integer instructions of SSE and AVX2 their EVEX forms, with a mask bit per byte or word, and adds a few of its own (VPERMW, VPSLLVW, VDBPSADBW, the moves between masks and vectors). A zmm register holds 64 bytes, so BW also brought the 32-bit and 64-bit mask instructions. CPUID leaf 7, sub-leaf 0, EBX bit 30.
• AVX-512 DQ (dword and qword) adds the floating-point logic instructions, conversions between floating point and 64-bit integers, VPMULLQ, the two-element and eight-element broadcasts, inserts and extracts, VRANGE, VREDUCE and VFPCLASS. It brought the 8-bit mask instructions. EBX bit 17.
• AVX-512 CD (conflict detection) finds equal elements in a vector, so that a loop that scatters to computed addresses can see where two lanes would write the same place. EBX bit 28.

CD came first, with AVX-512 F, in Intel’s Xeon Phi Knights Landing (2016). BW and DQ came with the Skylake-SP Xeons and Skylake-X Core i9s (2017), together with AVX512VL, and every later AVX-512 processor has all three, AMD’s Zen 4 and Zen 5 included. Xeon Phi never had BW or DQ.

The tables give the 512-bit form. Unless a row says otherwise, each packed instruction also has 128-bit and 256-bit forms, which need AVX512VL as well (CPUID EBX bit 31). The instructions with fixed xmm operands (VPEXTRB, VPINSRW and the rest) are EVEX.128 only.

The instructions

Byte and word arithmetic (BW)

Byte and word shifts (BW)

As in AVX-512 F, the immediate forms take their destination from EVEX.vvvv.

Byte and word compares and tests (BW)

These write a mask with a bit per byte or word. VPCMPB and its kin take the predicate in imm8 bits 2–0, as VPCMPD does (0 eq, 1 lt, 2 le, 3 false, 4 neq, 5 nlt, 6 nle, 7 true); the disassembler shows predicates 0, 1, 2, 4, 5 and 6 by name.

Byte and word moves, shuffles and packs (BW)

Between masks and vectors (BW, DQ)

Floating-point logic and VPMULLQ (DQ)

Conversions with 64-bit integers (DQ)

As in AVX-512 F, the conversions with a t truncate, and a value that does not fit gives the integer indefinite value.

Broadcast, insert and extract (DQ)

Range, reduce and classify (DQ)

Conflict detection (CD)

Notes

• The byte and word instructions cannot broadcast: their tuple type is Full Mem. VPACKSSDW and VPACKUSDW, whose sources are dwords, can.
• VPSRLW, VPSRAW and VPSLLW by an xmm count (66 0F D1, E1 and F1) and VPALIGNR (66 0F 3A 0F) ignore EVEX.W, as Intel’s manual writes them (WIG). LLVM 21 decodes only the W0 forms; our decoder takes both.
• Outside 64-bit mode, Intel’s manual gives the W1 forms VBROADCASTF64X2, VBROADCASTI64X2, VINSERTF64X2 and VEXTRACTF64X2 (and their integer partners) as valid. LLVM 21 shows them there as the W0 instructions (VBROADCASTF32X4 …); our decoder follows Intel.
• None of these instructions changes the flags.

Links