x86 Instruction Set – AVX-512 mask registers

Introduction

AVX-512 added eight opmask registers, k0 to k7. Each bit of a mask belongs to one element of a vector. An EVEX instruction can name a mask in its destination, {k1}, so that only the elements whose bits are set are written; and the compare and test instructions write their results into a mask, one bit per element. How masking, zeroing and the EVEX fields work is explained on the AVX-512 Foundation page.

The registers are 64 bits wide. The instructions on this page work on 8, 16, 32 or 64 of those bits, named by the last letter of the mnemonic: b, w, d or q. A write clears every bit above the size it writes. The sizes came with different sets:

• AVX-512 F (Intel Xeon Phi Knights Landing, 2016) has the 16-bit forms (KANDW, KMOVW …), enough for the 16 dwords of a zmm register;
• AVX-512 DQ (Intel Skylake-SP, 2017) adds the 8-bit forms, KADDW and KTESTW;
• AVX-512 BW (Skylake-SP, 2017) adds the 32-bit and 64-bit forms, for the 64 bytes of a zmm register.

k0 is special only as a write mask: the EVEX encoding 000 in the mask field means “no mask”, so {k0} cannot be written. The instructions on this page can read and write k0 like any other mask register.

These instructions are VEX-encoded, in the 0F map (and 0F 3A for the shifts). Their register operands are all in ModRM.mod = 11 forms, except KMOV, which can load and store memory and move to and from the general registers. A program checks for them as for their sets: CPUID leaf 7, sub-leaf 0, EBX bit 16 (AVX-512 F), bit 17 (DQ) and bit 30 (BW). The operating system must also have enabled the opmask state, XCR0 bit 5, with the other AVX-512 state (bits 6 and 7), which XGETBV reads.

The general-register forms of KMOV also have an EVEX encoding, added by APX so that they can reach the registers r16 to r31. Those are on the APX page.

The instructions

In the Forms column, k1 is ModRM.reg, k2 is VEX.vvvv in the three-operand forms and ModRM.rm in the two-operand ones, and k3 is ModRM.rm.

Logic

Arithmetic, shifts and unpacking

Tests

These two set the flags and write no register. OF, SF, AF and PF are cleared.

Moves

Notes

• Only KORTEST and KTEST change the flags. The rest leave them alone.
• The register forms need ModRM.mod = 11, and only KMOV at 90 and 91 takes memory. Intel’s manual gives the three-operand forms with VEX.L = 1 and the others with VEX.L = 0; our decoder shows the other value as an invalid instruction.
• KMOV at 92 and 93 with VEX.W = 1 and no F2 prefix is not an instruction.
• The decoder’s text follows LLVM’s (llvm-objdump, Intel syntax) for every form here.

Links