x86 Instruction Set – SSE2

Introduction

SSE2 came with Intel’s Pentium 4 in 2000. It uses the same registers and state as SSE (XMM0 to XMM7, XMM0 to XMM15 in 64-bit mode, and MXCSR) and adds two kinds of work to them:

double-precision floating point: two 64-bit values per register. The packed forms end in pd and take a 66 prefix; the scalar forms end in sd, take F2 and work on the low value only;
128-bit integer SIMD: the MMX instructions with a 66 prefix work on XMM registers instead of MMX registers, on sixteen bytes, eight words, four doublewords or two quadwords. SSE2 also added new integer instructions, such as paddq, pmuludq and pshufd.

It also brought conversions between the integer and floating-point types, non-temporal stores, and lfence, mfence, clflush and pause, which are described on the cache and memory ordering and flags and miscellaneous pages.

A program checks for SSE2 with CPUID leaf 1: EDX bit 26. The operating system must have enabled SSE (CR4.OSFXSR and CR4.OSXMMEXCPT, as on the SSE page). Every x86-64 processor has SSE2, and the 64-bit calling conventions pass floating-point values in the XMM registers.

Most of these instructions also have a VEX form, which came with AVX: its name starts with v and it is described on the AVX page. Each row below links to it.

The instructions

In the forms, xmm1 is the ModRM.reg operand and xmm2/m128 the ModRM.r/m operand. NP means that no 66, F2 or F3 prefix may be present.

Double-precision moves

Instruction	Forms	Encoding	What it does	Set
`movapd`	`xmm1, xmm2/m128` `xmm2/m128, xmm1`	`66 0F 28 /r` `66 0F 29 /r`	Moves two packed double-precision values. Memory must be 16-byte aligned. VEX form: `vmovapd`.	SSE2 (Intel Pentium 4, 2000)
`movupd`	`xmm1, xmm2/m128` `xmm2/m128, xmm1`	`66 0F 10 /r` `66 0F 11 /r`	Moves two packed double-precision values; memory need not be aligned. VEX form: `vmovupd`.	SSE2 (Intel Pentium 4, 2000)
`movsd`	`xmm1, xmm2/m64` `xmm2/m64, xmm1`	`F2 0F 10 /r` `F2 0F 11 /r`	Moves the low double-precision value. A load from memory zeroes bits 127:64; a move between registers leaves them unchanged. Not the string move `movsd` (A5). VEX form: `vmovsd`.	SSE2 (Intel Pentium 4, 2000)
`movlpd`	`xmm1, m64` `m64, xmm1`	`66 0F 12 /r` `66 0F 13 /r`	Loads or stores the low double-precision value; the high half is unchanged. Memory only. VEX form: `vmovlpd`.	SSE2 (Intel Pentium 4, 2000)
`movhpd`	`xmm1, m64` `m64, xmm1`	`66 0F 16 /r` `66 0F 17 /r`	Loads or stores the high double-precision value; the low half is unchanged. Memory only. VEX form: `vmovhpd`.	SSE2 (Intel Pentium 4, 2000)
`movmskpd`	`r32, xmm`	`66 0F 50 /r`	Copies the sign bits of the two values to bits 1:0 of a general register and zeroes the rest. VEX form: `vmovmskpd`.	SSE2 (Intel Pentium 4, 2000)

Double-precision arithmetic

Instruction	Forms	Encoding	What it does	Set
`addpd`	`xmm1, xmm2/m128`	`66 0F 58 /r`	Adds two packed double-precision values. VEX form: `vaddpd`.	SSE2 (Intel Pentium 4, 2000)
`addsd`	`xmm1, xmm2/m64`	`F2 0F 58 /r`	Adds the low values; the high value is unchanged. VEX form: `vaddsd`.	SSE2 (Intel Pentium 4, 2000)
`subpd`	`xmm1, xmm2/m128`	`66 0F 5C /r`	Subtracts the second operand’s values from the first’s. VEX form: `vsubpd`.	SSE2 (Intel Pentium 4, 2000)
`subsd`	`xmm1, xmm2/m64`	`F2 0F 5C /r`	Subtracts the low values. VEX form: `vsubsd`.	SSE2 (Intel Pentium 4, 2000)
`mulpd`	`xmm1, xmm2/m128`	`66 0F 59 /r`	Multiplies two packed values. VEX form: `vmulpd`.	SSE2 (Intel Pentium 4, 2000)
`mulsd`	`xmm1, xmm2/m64`	`F2 0F 59 /r`	Multiplies the low values. VEX form: `vmulsd`.	SSE2 (Intel Pentium 4, 2000)
`divpd`	`xmm1, xmm2/m128`	`66 0F 5E /r`	Divides the first operand’s values by the second’s. VEX form: `vdivpd`.	SSE2 (Intel Pentium 4, 2000)
`divsd`	`xmm1, xmm2/m64`	`F2 0F 5E /r`	Divides the low values. VEX form: `vdivsd`.	SSE2 (Intel Pentium 4, 2000)
`sqrtpd`	`xmm1, xmm2/m128`	`66 0F 51 /r`	Square roots of the two source values. VEX form: `vsqrtpd`.	SSE2 (Intel Pentium 4, 2000)
`sqrtsd`	`xmm1, xmm2/m64`	`F2 0F 51 /r`	Square root of the low source value. VEX form: `vsqrtsd`.	SSE2 (Intel Pentium 4, 2000)
`maxpd`	`xmm1, xmm2/m128`	`66 0F 5F /r`	The larger of each pair. If both are zero, or either is a NaN, the second operand’s value is returned. VEX form: `vmaxpd`.	SSE2 (Intel Pentium 4, 2000)
`maxsd`	`xmm1, xmm2/m64`	`F2 0F 5F /r`	The larger of the low values, with the same rule. VEX form: `vmaxsd`.	SSE2 (Intel Pentium 4, 2000)
`minpd`	`xmm1, xmm2/m128`	`66 0F 5D /r`	The smaller of each pair, with the same rule. VEX form: `vminpd`.	SSE2 (Intel Pentium 4, 2000)
`minsd`	`xmm1, xmm2/m64`	`F2 0F 5D /r`	The smaller of the low values, with the same rule. VEX form: `vminsd`.	SSE2 (Intel Pentium 4, 2000)

Double-precision comparisons

CMPPD and CMPSD write a mask of all ones where the comparison is true and all zeros where it is false. The immediate picks the comparison: 0 equal, 1 less than, 2 less or equal, 3 unordered, 4 not equal, 5 not less than, 6 not less or equal, 7 ordered. The disassembler, as LLVM does, shows these eight as their own names and any other immediate as a number.

Instruction	Forms	Encoding	What it does	Set
`cmppd`	`xmm1, xmm2/m128, imm8`	`66 0F C2 /r ib`	Compares two pairs of double-precision values with the predicate in imm8. Predicate names: `cmpeqpd` (0), `cmpltpd` (1), `cmplepd` (2), `cmpunordpd` (3), `cmpneqpd` (4), `cmpnltpd` (5), `cmpnlepd` (6), `cmpordpd` (7). VEX form: `vcmppd`, with 32 predicates.	SSE2 (Intel Pentium 4, 2000)
`cmpsd`	`xmm1, xmm2/m64, imm8`	`F2 0F C2 /r ib`	Compares the low values and writes the mask to the low element; the high one is unchanged. Not the string compare `cmpsd` (A7). Predicate names: `cmpeqsd` (0), `cmpltsd` (1), `cmplesd` (2), `cmpunordsd` (3), `cmpneqsd` (4), `cmpnltsd` (5), `cmpnlesd` (6), `cmpordsd` (7). VEX form: `vcmpsd`.	SSE2 (Intel Pentium 4, 2000)
`comisd`	`xmm1, xmm2/m64`	`66 0F 2F /r`	Compares the low values and sets ZF, PF and CF (all three for unordered); clears OF, SF and AF. Signals invalid on any NaN. VEX form: `vcomisd`.	SSE2 (Intel Pentium 4, 2000)
`ucomisd`	`xmm1, xmm2/m64`	`66 0F 2E /r`	As `comisd`, but signals invalid only on a signalling NaN. VEX form: `vucomisd`.	SSE2 (Intel Pentium 4, 2000)

Double-precision logic, shuffles and unpacking

Instruction	Forms	Encoding	What it does	Set
`andpd`	`xmm1, xmm2/m128`	`66 0F 54 /r`	Bitwise AND. VEX form: `vandpd`.	SSE2 (Intel Pentium 4, 2000)
`andnpd`	`xmm1, xmm2/m128`	`66 0F 55 /r`	Bitwise AND of the inverted first operand with the second. VEX form: `vandnpd`.	SSE2 (Intel Pentium 4, 2000)
`orpd`	`xmm1, xmm2/m128`	`66 0F 56 /r`	Bitwise OR. VEX form: `vorpd`.	SSE2 (Intel Pentium 4, 2000)
`xorpd`	`xmm1, xmm2/m128`	`66 0F 57 /r`	Bitwise exclusive OR. VEX form: `vxorpd`.	SSE2 (Intel Pentium 4, 2000)
`shufpd`	`xmm1, xmm2/m128, imm8`	`66 0F C6 /r ib`	The low result is the first operand’s value chosen by imm8 bit 0; the high result is the second operand’s value chosen by bit 1. VEX form: `vshufpd`.	SSE2 (Intel Pentium 4, 2000)
`unpcklpd`	`xmm1, xmm2/m128`	`66 0F 14 /r`	The low values of both operands: a0, b0. VEX form: `vunpcklpd`.	SSE2 (Intel Pentium 4, 2000)
`unpckhpd`	`xmm1, xmm2/m128`	`66 0F 15 /r`	The high values of both operands: a1, b1. VEX form: `vunpckhpd`.	SSE2 (Intel Pentium 4, 2000)

Conversions

Conversions to integers round by MXCSR.RC; the cvtt forms truncate towards zero. A value out of range, or a NaN, gives the integer indefinite value, 80000000h (8000000000000000h for 64 bits). Where a result is narrower than the register, the unused upper part is zeroed, except for the scalar forms, which keep the destination’s other elements.

Instruction	Forms	Encoding	What it does	Set
`cvtps2pd`	`xmm1, xmm2/m64`	`NP 0F 5A /r`	Two single-precision values to two double-precision values. VEX form: `vcvtps2pd`.	SSE2 (Intel Pentium 4, 2000)
`cvtpd2ps`	`xmm1, xmm2/m128`	`66 0F 5A /r`	Two double-precision values to two single-precision values in the low half. VEX form: `vcvtpd2ps`.	SSE2 (Intel Pentium 4, 2000)
`cvtss2sd`	`xmm1, xmm2/m32`	`F3 0F 5A /r`	The low single-precision value to double precision. VEX form: `vcvtss2sd`.	SSE2 (Intel Pentium 4, 2000)
`cvtsd2ss`	`xmm1, xmm2/m64`	`F2 0F 5A /r`	The low double-precision value to single precision. VEX form: `vcvtsd2ss`.	SSE2 (Intel Pentium 4, 2000)
`cvtdq2ps`	`xmm1, xmm2/m128`	`NP 0F 5B /r`	Four signed 32-bit integers to single precision. VEX form: `vcvtdq2ps`.	SSE2 (Intel Pentium 4, 2000)
`cvtps2dq`	`xmm1, xmm2/m128`	`66 0F 5B /r`	Four single-precision values to signed 32-bit integers. VEX form: `vcvtps2dq`.	SSE2 (Intel Pentium 4, 2000)
`cvttps2dq`	`xmm1, xmm2/m128`	`F3 0F 5B /r`	As `cvtps2dq`, truncating. VEX form: `vcvttps2dq`.	SSE2 (Intel Pentium 4, 2000)
`cvtdq2pd`	`xmm1, xmm2/m64`	`F3 0F E6 /r`	Two signed 32-bit integers to double precision. VEX form: `vcvtdq2pd`.	SSE2 (Intel Pentium 4, 2000)
`cvtpd2dq`	`xmm1, xmm2/m128`	`F2 0F E6 /r`	Two double-precision values to signed 32-bit integers in the low quadword. VEX form: `vcvtpd2dq`.	SSE2 (Intel Pentium 4, 2000)
`cvttpd2dq`	`xmm1, xmm2/m128`	`66 0F E6 /r`	As `cvtpd2dq`, truncating. VEX form: `vcvttpd2dq`.	SSE2 (Intel Pentium 4, 2000)
`cvtpi2pd`	`xmm, mm/m64`	`66 0F 2A /r`	Two signed 32-bit integers from an MMX register or memory to double precision.	SSE2 (Intel Pentium 4, 2000)
`cvtpd2pi`	`mm, xmm/m128`	`66 0F 2D /r`	Two double-precision values to signed 32-bit integers in an MMX register.	SSE2 (Intel Pentium 4, 2000)
`cvttpd2pi`	`mm, xmm/m128`	`66 0F 2C /r`	As `cvtpd2pi`, truncating.	SSE2 (Intel Pentium 4, 2000)
`cvtsi2sd`	`xmm1, r/m32` `xmm1, r/m64`	`F2 0F 2A /r` `F2 REX.W 0F 2A /r`	A signed integer to the low double-precision value; the high value is unchanged. The 64-bit form is for 64-bit mode only. VEX form: `vcvtsi2sd`.	SSE2 (Intel Pentium 4, 2000)
`cvtsd2si`	`r32, xmm1/m64` `r64, xmm1/m64`	`F2 0F 2D /r` `F2 REX.W 0F 2D /r`	The low double-precision value to a signed integer. VEX form: `vcvtsd2si`.	SSE2 (Intel Pentium 4, 2000)
`cvttsd2si`	`r32, xmm1/m64` `r64, xmm1/m64`	`F2 0F 2C /r` `F2 REX.W 0F 2C /r`	As `cvtsd2si`, truncating. VEX form: `vcvttsd2si`.	SSE2 (Intel Pentium 4, 2000)

Integer moves

Instruction	Forms	Encoding	What it does	Set
`movd`	`xmm, r/m32` `r/m32, xmm`	`66 0F 6E /r` `66 0F 7E /r`	Moves a doubleword between a general register or memory and the low doubleword of an XMM register; a move into the XMM register zeroes bits 127:32. The MMX forms are on the MMX page. VEX form: `vmovd`.	SSE2 (Intel Pentium 4, 2000)
`movq`	`xmm1, xmm2/m64` `xmm2/m64, xmm1` `xmm, r/m64` `r/m64, xmm`	`F3 0F 7E /r` `66 0F D6 /r` `66 REX.W 0F 6E /r` `66 REX.W 0F 7E /r`	Moves a quadword to or from the low quadword of an XMM register; a move into the XMM register zeroes bits 127:64. The forms with a general register are for 64-bit mode only. The MMX forms are on the MMX page. VEX form: `vmovq`.	SSE2 (Intel Pentium 4, 2000)
`movdqa`	`xmm1, xmm2/m128` `xmm2/m128, xmm1`	`66 0F 6F /r` `66 0F 7F /r`	Moves 128 bits of integer data. Memory must be 16-byte aligned. VEX form: `vmovdqa`.	SSE2 (Intel Pentium 4, 2000)
`movdqu`	`xmm1, xmm2/m128` `xmm2/m128, xmm1`	`F3 0F 6F /r` `F3 0F 7F /r`	Moves 128 bits; memory need not be aligned. VEX form: `vmovdqu`.	SSE2 (Intel Pentium 4, 2000)
`movq2dq`	`xmm, mm`	`F3 0F D6 /r`	Copies an MMX register to the low quadword of an XMM register and zeroes bits 127:64.	SSE2 (Intel Pentium 4, 2000)
`movdq2q`	`mm, xmm`	`F2 0F D6 /r`	Copies the low quadword of an XMM register to an MMX register.	SSE2 (Intel Pentium 4, 2000)
`pmovmskb`	`r32, xmm`	`66 0F D7 /r`	Copies the top bit of each of the sixteen bytes to bits 15:0 of a general register and zeroes the rest. The MMX form is on the SSE page. VEX form: `vpmovmskb`.	SSE2 (Intel Pentium 4, 2000)
`pextrw`	`r32, xmm, imm8`	`66 0F C5 /r ib`	Copies the word selected by imm8[2:0] to a general register, zero-extended. SSE4.1 added a form that can store to memory, on the SSE4 page. VEX form: `vpextrw`.	SSE2 (Intel Pentium 4, 2000)
`pinsrw`	`xmm, r32/m16, imm8`	`66 0F C4 /r ib`	Writes the low word of the source into the word selected by imm8[2:0]. VEX form: `vpinsrw`.	SSE2 (Intel Pentium 4, 2000)

Integer arithmetic

Each of these works on every element of the register. Where a row names a 64-bit form, that is the MMX-register instruction with no prefix.

Instruction	Forms	Encoding	What it does	Set
`paddb`	`xmm1, xmm2/m128`	`66 0F FC /r`	Adds bytes, wrapping around. 64-bit form: MMX. VEX form: `vpaddb`.	SSE2 (Intel Pentium 4, 2000)
`paddw`	`xmm1, xmm2/m128`	`66 0F FD /r`	Adds words, wrapping around. 64-bit form: MMX. VEX form: `vpaddw`.	SSE2 (Intel Pentium 4, 2000)
`paddd`	`xmm1, xmm2/m128`	`66 0F FE /r`	Adds doublewords, wrapping around. 64-bit form: MMX. VEX form: `vpaddd`.	SSE2 (Intel Pentium 4, 2000)
`paddq`	`mm1, mm2/m64` `xmm1, xmm2/m128`	`NP 0F D4 /r` `66 0F D4 /r`	Adds quadwords, wrapping around. Both forms are new in SSE2. VEX form: `vpaddq`.	SSE2 (Intel Pentium 4, 2000)
`paddsb`	`xmm1, xmm2/m128`	`66 0F EC /r`	Adds signed bytes with saturation. 64-bit form: MMX. VEX form: `vpaddsb`.	SSE2 (Intel Pentium 4, 2000)
`paddsw`	`xmm1, xmm2/m128`	`66 0F ED /r`	Adds signed words with saturation. 64-bit form: MMX. VEX form: `vpaddsw`.	SSE2 (Intel Pentium 4, 2000)
`paddusb`	`xmm1, xmm2/m128`	`66 0F DC /r`	Adds unsigned bytes with saturation. 64-bit form: MMX. VEX form: `vpaddusb`.	SSE2 (Intel Pentium 4, 2000)
`paddusw`	`xmm1, xmm2/m128`	`66 0F DD /r`	Adds unsigned words with saturation. 64-bit form: MMX. VEX form: `vpaddusw`.	SSE2 (Intel Pentium 4, 2000)
`psubb`	`xmm1, xmm2/m128`	`66 0F F8 /r`	Subtracts bytes, wrapping around. 64-bit form: MMX. VEX form: `vpsubb`.	SSE2 (Intel Pentium 4, 2000)
`psubw`	`xmm1, xmm2/m128`	`66 0F F9 /r`	Subtracts words, wrapping around. 64-bit form: MMX. VEX form: `vpsubw`.	SSE2 (Intel Pentium 4, 2000)
`psubd`	`xmm1, xmm2/m128`	`66 0F FA /r`	Subtracts doublewords, wrapping around. 64-bit form: MMX. VEX form: `vpsubd`.	SSE2 (Intel Pentium 4, 2000)
`psubq`	`mm1, mm2/m64` `xmm1, xmm2/m128`	`NP 0F FB /r` `66 0F FB /r`	Subtracts quadwords, wrapping around. Both forms are new in SSE2. VEX form: `vpsubq`.	SSE2 (Intel Pentium 4, 2000)
`psubsb`	`xmm1, xmm2/m128`	`66 0F E8 /r`	Subtracts signed bytes with saturation. 64-bit form: MMX. VEX form: `vpsubsb`.	SSE2 (Intel Pentium 4, 2000)
`psubsw`	`xmm1, xmm2/m128`	`66 0F E9 /r`	Subtracts signed words with saturation. 64-bit form: MMX. VEX form: `vpsubsw`.	SSE2 (Intel Pentium 4, 2000)
`psubusb`	`xmm1, xmm2/m128`	`66 0F D8 /r`	Subtracts unsigned bytes with saturation. 64-bit form: MMX. VEX form: `vpsubusb`.	SSE2 (Intel Pentium 4, 2000)
`psubusw`	`xmm1, xmm2/m128`	`66 0F D9 /r`	Subtracts unsigned words with saturation. 64-bit form: MMX. VEX form: `vpsubusw`.	SSE2 (Intel Pentium 4, 2000)
`pmullw`	`xmm1, xmm2/m128`	`66 0F D5 /r`	Multiplies words and keeps the low 16 bits of each product. 64-bit form: MMX. VEX form: `vpmullw`.	SSE2 (Intel Pentium 4, 2000)
`pmulhw`	`xmm1, xmm2/m128`	`66 0F E5 /r`	Multiplies signed words and keeps the high 16 bits of each product. 64-bit form: MMX. VEX form: `vpmulhw`.	SSE2 (Intel Pentium 4, 2000)
`pmulhuw`	`xmm1, xmm2/m128`	`66 0F E4 /r`	Multiplies unsigned words and keeps the high 16 bits of each product. 64-bit form: SSE. VEX form: `vpmulhuw`.	SSE2 (Intel Pentium 4, 2000)
`pmuludq`	`mm1, mm2/m64` `xmm1, xmm2/m128`	`NP 0F F4 /r` `66 0F F4 /r`	Multiplies the unsigned low doubleword of each quadword and writes the 64-bit products. Both forms are new in SSE2. VEX form: `vpmuludq`.	SSE2 (Intel Pentium 4, 2000)
`pmaddwd`	`xmm1, xmm2/m128`	`66 0F F5 /r`	Multiplies signed words and adds each adjacent pair of 32-bit products into a doubleword. 64-bit form: MMX. VEX form: `vpmaddwd`.	SSE2 (Intel Pentium 4, 2000)
`pavgb`	`xmm1, xmm2/m128`	`66 0F E0 /r`	Rounded average of unsigned bytes. 64-bit form: SSE. VEX form: `vpavgb`.	SSE2 (Intel Pentium 4, 2000)
`pavgw`	`xmm1, xmm2/m128`	`66 0F E3 /r`	Rounded average of unsigned words. 64-bit form: SSE. VEX form: `vpavgw`.	SSE2 (Intel Pentium 4, 2000)
`pmaxsw`	`xmm1, xmm2/m128`	`66 0F EE /r`	Maximum of signed words. 64-bit form: SSE. VEX form: `vpmaxsw`.	SSE2 (Intel Pentium 4, 2000)
`pmaxub`	`xmm1, xmm2/m128`	`66 0F DE /r`	Maximum of unsigned bytes. 64-bit form: SSE. VEX form: `vpmaxub`.	SSE2 (Intel Pentium 4, 2000)
`pminsw`	`xmm1, xmm2/m128`	`66 0F EA /r`	Minimum of signed words. 64-bit form: SSE. VEX form: `vpminsw`.	SSE2 (Intel Pentium 4, 2000)
`pminub`	`xmm1, xmm2/m128`	`66 0F DA /r`	Minimum of unsigned bytes. 64-bit form: SSE. VEX form: `vpminub`.	SSE2 (Intel Pentium 4, 2000)
`psadbw`	`xmm1, xmm2/m128`	`66 0F F6 /r`	Sums the absolute differences of unsigned bytes in each 64-bit half; the two sums go to bits 15:0 and 79:64, and the rest is zeroed. 64-bit form: SSE. VEX form: `vpsadbw`.	SSE2 (Intel Pentium 4, 2000)

Integer comparisons and logic

Instruction	Forms	Encoding	What it does	Set
`pcmpeqb`	`xmm1, xmm2/m128`	`66 0F 74 /r`	Sets each byte to all ones where the bytes are equal, all zeros where not. 64-bit form: MMX. VEX form: `vpcmpeqb`.	SSE2 (Intel Pentium 4, 2000)
`pcmpeqw`	`xmm1, xmm2/m128`	`66 0F 75 /r`	The same for words. 64-bit form: MMX. VEX form: `vpcmpeqw`.	SSE2 (Intel Pentium 4, 2000)
`pcmpeqd`	`xmm1, xmm2/m128`	`66 0F 76 /r`	The same for doublewords. 64-bit form: MMX. VEX form: `vpcmpeqd`.	SSE2 (Intel Pentium 4, 2000)
`pcmpgtb`	`xmm1, xmm2/m128`	`66 0F 64 /r`	Sets each byte to all ones where the first operand’s signed byte is greater. 64-bit form: MMX. VEX form: `vpcmpgtb`.	SSE2 (Intel Pentium 4, 2000)
`pcmpgtw`	`xmm1, xmm2/m128`	`66 0F 65 /r`	The same for signed words. 64-bit form: MMX. VEX form: `vpcmpgtw`.	SSE2 (Intel Pentium 4, 2000)
`pcmpgtd`	`xmm1, xmm2/m128`	`66 0F 66 /r`	The same for signed doublewords. 64-bit form: MMX. VEX form: `vpcmpgtd`.	SSE2 (Intel Pentium 4, 2000)
`pand`	`xmm1, xmm2/m128`	`66 0F DB /r`	Bitwise AND. 64-bit form: MMX. VEX form: `vpand`.	SSE2 (Intel Pentium 4, 2000)
`pandn`	`xmm1, xmm2/m128`	`66 0F DF /r`	Bitwise AND of the inverted first operand with the second. 64-bit form: MMX. VEX form: `vpandn`.	SSE2 (Intel Pentium 4, 2000)
`por`	`xmm1, xmm2/m128`	`66 0F EB /r`	Bitwise OR. 64-bit form: MMX. VEX form: `vpor`.	SSE2 (Intel Pentium 4, 2000)
`pxor`	`xmm1, xmm2/m128`	`66 0F EF /r`	Bitwise exclusive OR. 64-bit form: MMX. VEX form: `vpxor`.	SSE2 (Intel Pentium 4, 2000)

Shifts

The element shifts take their count from the low 64 bits of an XMM register or memory, or from an immediate. A count wider than the element clears it, for the logical shifts, or fills it with the sign bit, for the arithmetic ones.

Instruction	Forms	Encoding	What it does	Set
`psllw`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F F1 /r` `66 0F 71 /6 ib`	Shifts words left. 64-bit form: MMX. VEX form: `vpsllw`.	SSE2 (Intel Pentium 4, 2000)
`pslld`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F F2 /r` `66 0F 72 /6 ib`	Shifts doublewords left. 64-bit form: MMX. VEX form: `vpslld`.	SSE2 (Intel Pentium 4, 2000)
`psllq`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F F3 /r` `66 0F 73 /6 ib`	Shifts quadwords left. 64-bit form: MMX. VEX form: `vpsllq`.	SSE2 (Intel Pentium 4, 2000)
`psrlw`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F D1 /r` `66 0F 71 /2 ib`	Shifts words right, filling with zeros. 64-bit form: MMX. VEX form: `vpsrlw`.	SSE2 (Intel Pentium 4, 2000)
`psrld`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F D2 /r` `66 0F 72 /2 ib`	Shifts doublewords right, filling with zeros. 64-bit form: MMX. VEX form: `vpsrld`.	SSE2 (Intel Pentium 4, 2000)
`psrlq`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F D3 /r` `66 0F 73 /2 ib`	Shifts quadwords right, filling with zeros. 64-bit form: MMX. VEX form: `vpsrlq`.	SSE2 (Intel Pentium 4, 2000)
`psraw`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F E1 /r` `66 0F 71 /4 ib`	Shifts signed words right, filling with the sign bit. 64-bit form: MMX. VEX form: `vpsraw`.	SSE2 (Intel Pentium 4, 2000)
`psrad`	`xmm1, xmm2/m128` `xmm1, imm8`	`66 0F E2 /r` `66 0F 72 /4 ib`	Shifts signed doublewords right, filling with the sign bit. 64-bit form: MMX. VEX form: `vpsrad`.	SSE2 (Intel Pentium 4, 2000)
`pslldq`	`xmm1, imm8`	`66 0F 73 /7 ib`	Shifts the whole register left by imm8 bytes, filling with zeros; a count above 15 clears it. VEX form: `vpslldq`.	SSE2 (Intel Pentium 4, 2000)
`psrldq`	`xmm1, imm8`	`66 0F 73 /3 ib`	Shifts the whole register right by imm8 bytes, filling with zeros. VEX form: `vpsrldq`.	SSE2 (Intel Pentium 4, 2000)

Packing, unpacking and shuffles

Instruction	Forms	Encoding	What it does	Set
`packsswb`	`xmm1, xmm2/m128`	`66 0F 63 /r`	Narrows the signed words of both operands to signed bytes with saturation: the first operand’s fill the low half. 64-bit form: MMX. VEX form: `vpacksswb`.	SSE2 (Intel Pentium 4, 2000)
`packssdw`	`xmm1, xmm2/m128`	`66 0F 6B /r`	Narrows signed doublewords to signed words with saturation. 64-bit form: MMX. VEX form: `vpackssdw`.	SSE2 (Intel Pentium 4, 2000)
`packuswb`	`xmm1, xmm2/m128`	`66 0F 67 /r`	Narrows signed words to unsigned bytes with saturation. 64-bit form: MMX. VEX form: `vpackuswb`.	SSE2 (Intel Pentium 4, 2000)
`punpcklbw`	`xmm1, xmm2/m128`	`66 0F 60 /r`	Interleaves the low eight bytes of each operand. 64-bit form: MMX. VEX form: `vpunpcklbw`.	SSE2 (Intel Pentium 4, 2000)
`punpcklwd`	`xmm1, xmm2/m128`	`66 0F 61 /r`	Interleaves the low four words. 64-bit form: MMX. VEX form: `vpunpcklwd`.	SSE2 (Intel Pentium 4, 2000)
`punpckldq`	`xmm1, xmm2/m128`	`66 0F 62 /r`	Interleaves the low two doublewords. 64-bit form: MMX. VEX form: `vpunpckldq`.	SSE2 (Intel Pentium 4, 2000)
`punpcklqdq`	`xmm1, xmm2/m128`	`66 0F 6C /r`	The low quadwords of both operands. New in SSE2. VEX form: `vpunpcklqdq`.	SSE2 (Intel Pentium 4, 2000)
`punpckhbw`	`xmm1, xmm2/m128`	`66 0F 68 /r`	Interleaves the high eight bytes of each operand. 64-bit form: MMX. VEX form: `vpunpckhbw`.	SSE2 (Intel Pentium 4, 2000)
`punpckhwd`	`xmm1, xmm2/m128`	`66 0F 69 /r`	Interleaves the high four words. 64-bit form: MMX. VEX form: `vpunpckhwd`.	SSE2 (Intel Pentium 4, 2000)
`punpckhdq`	`xmm1, xmm2/m128`	`66 0F 6A /r`	Interleaves the high two doublewords. 64-bit form: MMX. VEX form: `vpunpckhdq`.	SSE2 (Intel Pentium 4, 2000)
`punpckhqdq`	`xmm1, xmm2/m128`	`66 0F 6D /r`	The high quadwords of both operands. New in SSE2. VEX form: `vpunpckhqdq`.	SSE2 (Intel Pentium 4, 2000)
`pshufd`	`xmm1, xmm2/m128, imm8`	`66 0F 70 /r ib`	Shuffles four doublewords: each 2-bit field of imm8 picks the source doubleword for one destination doubleword. VEX form: `vpshufd`.	SSE2 (Intel Pentium 4, 2000)
`pshufhw`	`xmm1, xmm2/m128, imm8`	`F3 0F 70 /r ib`	Shuffles the high four words by imm8 and copies the low quadword unchanged. VEX form: `vpshufhw`.	SSE2 (Intel Pentium 4, 2000)
`pshuflw`	`xmm1, xmm2/m128, imm8`	`F2 0F 70 /r ib`	Shuffles the low four words by imm8 and copies the high quadword unchanged. VEX form: `vpshuflw`.	SSE2 (Intel Pentium 4, 2000)

Non-temporal stores

These store without bringing the line into the caches, through write-combining. The stores are weakly ordered: sfence or mfence orders them.

Instruction	Forms	Encoding	What it does	Set
`movntpd`	`m128, xmm1`	`66 0F 2B /r`	Stores two double-precision values with a non-temporal hint. Memory must be 16-byte aligned. VEX form: `vmovntpd`.	SSE2 (Intel Pentium 4, 2000)
`movntdq`	`m128, xmm1`	`66 0F E7 /r`	Stores 128 bits of integer data with a non-temporal hint. Memory must be 16-byte aligned. VEX form: `vmovntdq`.	SSE2 (Intel Pentium 4, 2000)
`movnti`	`m32, r32` `m64, r64`	`NP 0F C3 /r` `NP REX.W 0F C3 /r`	Stores a general register with a non-temporal hint. The 64-bit form is for 64-bit mode only.	SSE2 (Intel Pentium 4, 2000)
`maskmovdqu`	`xmm1, xmm2`	`66 0F F7 /r`	Stores the bytes of xmm1 whose mask byte in xmm2 has its top bit set, to DS:[DI], [EDI] or [RDI] by the address size, with a non-temporal hint. VEX form: `vmaskmovdqu`.	SSE2 (Intel Pentium 4, 2000)

Notes

Alignment. In the legacy encodings a 128-bit memory operand must be 16-byte aligned, or the instruction raises #GP. movupd, movdqu, maskmovdqu and the 64-bit and 32-bit memory operands are the exceptions.
Exceptions. The floating-point instructions set the exception flags in MXCSR. An unmasked exception raises #XM when CR4.OSXMMEXCPT is set, and #UD when it is not. The integer instructions raise no floating-point exceptions.
Prefixes. The 66, F2 and F3 prefixes are part of the opcode here. The 66 prefix does not change the operand size of these instructions, and REX.W changes it only where a general register or a 64-bit form is named above.
Two names. movsd and cmpsd are also the names of string instructions. The disassembler tells them apart by the opcode: these have 0F before them.