x86 Instruction Set – Later AVX-512 extensions

Introduction

AVX-512 grew set by set. This page has the smaller sets that came after, or beside, Foundation, BW, DQ and CD. All of them use the zmm and mask registers and the EVEX encoding, with masking, broadcast and disp8×N as explained on the AVX-512 Foundation page, where the tuple types after the encodings below are defined too. Each set has its own CPUID bit, in leaf 7, and a program checks for it as well as for AVX-512 F. Unless a row says otherwise, the sets after the Xeon Phi ones also have 128-bit and 256-bit forms with AVX512VL; the tables give the 512-bit form.

The Xeon Phi sets

ER, PF, 4FMAPS and 4VNNIW exist only on Intel’s Xeon Phi processors: ER and PF on Knights Landing (x200, launched in June 2016) and on Knights Mill, and 4FMAPS and 4VNNIW on Knights Mill (x205, from December 2017) alone. No other processor, from Intel or AMD, has them. Their instructions are 512-bit only, or scalar.

• Intel ended Knights Landing in 2018: the last orders were taken on 31 August 2018 and the last chips shipped on 19 July 2019.
• Knights Mill, the last Xeon Phi, followed in 2019: last orders on 9 August 2019, last shipments on 31 July 2020.
• The compilers have since dropped them: LLVM 19 (2024) removed its support for these sets, after deprecating it in LLVM 18, and GCC 15 did the same. LLVM 21’s disassembler still decodes the instructions, and so does ours.

The later sets

• IFMA and VBMI came with Cannon Lake (2018), VNNI with the Cascade Lake Xeons (2019), and VBMI2, BITALG and VPOPCNTDQ with Ice Lake (2019), which had IFMA and VBMI too. Tiger Lake, Rocket Lake, the Ice Lake-SP Xeons and the Xeons from Sapphire Rapids on have all six, and so do AMD’s Zen 4 (2022) and Zen 5 (2024). The Cooper Lake Xeons, built on Cascade Lake, have VNNI but not the others.
• BF16 came with the Cooper Lake Xeons (2020); Sapphire Rapids (2023) and Zen 4 have it too.
• VP2INTERSECT came with Tiger Lake (2020). Intel’s server processors that followed (Sapphire Rapids and later) do not have it; AMD added it with Zen 5 (2024).
• Intel’s hybrid client processors from Alder Lake on have no AVX-512 at all (see AVX-512 Foundation). VNNI and IFMA came back to them in VEX form, as AVX-VNNI and AVX-IFMA.

The instructions

Exponential and reciprocal approximations (ER)

Gather and scatter prefetches (PF)

These prefetch the cache lines that a gather or scatter with the same operands would touch, for the elements whose mask bits are set, and load nothing into a register. pf0 prefetches with the T0 hint (into every cache level) and pf1 with T1; the scatter forms prefetch with the intent to write. They address memory with VSIB, as the gathers do, need a mask other than k0, and use ModRM.reg as part of the opcode.

Four-iteration multiply-add and dot product (4FMAPS, 4VNNIW)

Each of these works through a block of four source registers, written zmm2+3: EVEX.vvvv names the first, and its low two bits are ignored, so the block is zmm0–3, zmm4–7 and so on. Memory holds four elements, one for each register, and each is broadcast in turn. The memory operand is 16 bytes, and disp8 is scaled by 16 (Intel’s Tuple1_4X).

52-bit integer multiply-add (IFMA)

Byte permutes (VBMI)

Compress, expand and double shifts (VBMI2)

The double shifts join an element of two registers, shift the pair and keep half, as SHLD and SHRD do for general registers. The shift count is taken modulo the element size.

Dot products (VNNI)

Population counts and bit shuffle (BITALG, VPOPCNTDQ)

bfloat16 (BF16)

bfloat16 is the top half of a single: a sign, the same 8-bit exponent and a 7-bit fraction. These conversions round to nearest even and raise no exceptions.

Intersection (VP2INTERSECT)

Notes

• The ER and PF instructions are 512-bit only (the scalar ER ones ignore the length); 4FMAPS and 4VNNIW are 512-bit or scalar. Our decoder shows their other lengths as invalid.
• For the PF prefetches, LLVM writes the mask as an operand of its own, vgatherpf0dps {k1}, dword ptr [...]. Intel’s manual writes it on the memory operand, VGATHERPF0DPS vm32z {k1}, and so does our decoder.
• VP2INTERSECT always writes an even mask register and the one after it (k0 and k1, k2 and k3 …), and the disassembly names the even one.
• The EVEX forms of GFNI, VAES and VPCLMULQDQ, which came with Ice Lake too, are on the cryptography page.
• None of these instructions changes the flags.

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