x86 Instruction Set – SSE

Introduction

SSE (Streaming SIMD Extensions) came with Intel’s Pentium III in 1999. It does arithmetic on four single-precision (32-bit) floating-point numbers at once. AMD added it with the Athlon XP in 2001.

SSE brought new registers and state:

• eight 128-bit registers, XMM0 to XMM7, each holding four single-precision values. In 64-bit mode a REX prefix reaches eight more, XMM8 to XMM15;
• MXCSR, a 32-bit control and status register. It holds the rounding mode, the flush-to-zero bit, the six exception masks and the six exception flags. Later processors added the denormals-are-zero bit.

Each arithmetic instruction has a packed form, whose name ends in ps and which works on all four values, and a scalar form, ending in ss, which works on the lowest value only and leaves the other three unchanged. SSE also added integer instructions on the 64-bit MMX registers (pavgb, pshufw and the rest) and cacheability instructions such as movntq. Its prefetch instructions and sfence are described on the cache and memory ordering page; the double-precision and 128-bit integer forms came with SSE2.

A program checks for SSE with CPUID leaf 1: EDX bit 25. The operating system must also have enabled it: it sets CR4.OSFXSR (bit 9) to say that it saves the XMM registers with FXSAVE, and CR4.OSXMMEXCPT (bit 10) to take SIMD floating-point exceptions as #XM. Without OSFXSR the SSE instructions raise #UD.

Most of these instructions also have a VEX form, which came with AVX: its name starts with v, it takes a separate destination and it is described on the AVX page. Each row below links to it.

The instructions

In the forms, xmm1 is the ModRM.reg operand and xmm2/m128 the ModRM.r/m operand. NP means that no 66, F2 or F3 prefix may be present: with one, the same opcode is another instruction.

Notes

• Alignment. In the legacy encodings a 128-bit memory operand must be 16-byte aligned, or the instruction raises #GP. movups and the 64-bit and 32-bit memory operands are the exceptions. The VEX forms drop the rule, except for vmovaps and vmovntps.
• Exceptions. The arithmetic, comparisons and conversions set the exception flags in MXCSR. An unmasked exception raises #XM when CR4.OSXMMEXCPT is set, and #UD when it is not.
• Upper bits. A legacy SSE instruction leaves bits 255:128 of the YMM register (and above) unchanged; a VEX form zeroes them. Mixing the two on processors with AVX can cost a state transition, which is why compilers use vzeroupper.
• Decoding. 0F 12 and 0F 16 with a 66 prefix and a register operand have no movlpd or movhpd form; the disassembler, as LLVM does, shows them as movhlps and movlhps.

Links