Raw Machine Code: the CPU list

Introduction

The viewer’s CPU choice is made from a registry of decoders (a folder of small adapter files, one for each CPU), so this list is the registry as it stands: 25 CPUs in 14 families. Each row gives the variants the Variant / mode choice offers, the byte order, the options that appear while the CPU is chosen, and the page that describes the instruction set. The variant you choose decides which instructions are valid, and how an instruction of a later model is shown (as undocumented, unavailable or illegal, depending on the CPU), so choose it as carefully as the CPU.

Byte order is stated for every CPU. Where a CPU runs in both orders a Byte order option appears and the usual order for the chip is its default.

x86

CPU	Variants	Byte order	Options
x86 and x86-64	64-bit (x86-64); 32-bit (IA-32, the starting choice); 16-bit (real mode)	Little-endian	None

ARM

CPU	Variants	Byte order	Options
AArch64	A64 with every extension	Little-endian	None
ARM, Thumb and Thumb-2 (32-bit)	ARM state (A32); Thumb state (T16 and T32). The whole region is read in the state chosen	Little-endian	Architecture (ARMv4T to ARMv8-A and the M profiles); VFP and Advanced SIMD; pseudo-instructions

RISC-V

CPU	Variants	Byte order	Options
RISC-V	RV64 and RV32 with every extension; RV64GC (the starting choice) and RV32GC; RV64IMAC; RV32IMAC; RV32IMC; RV32IM; RV32I; RV64I; RV32E; RV32 with Zcb, Zcmp, Zcmt and Zb*; RV64GCV with Zba, Zbb and Zbs	Little-endian	Register names (ABI or numbers); pseudo-instructions

MIPS

CPU	Variants	Byte order	Options
MIPS	MIPS I to V; MIPS32 and MIPS64 releases 1, 2, 5 and 6 (MIPS32 release 2 is the starting choice); the PlayStation R3000A with the GTE (`ps1`); the Nintendo 64 VR4300 (`vr4300`)	Both; the chip’s usual order is the default (PlayStation little, N64 big, otherwise big)	Register names (o32, n32 and n64, or numbers); pseudo-instructions

PowerPC

CPU	Variants	Byte order	Options
PowerPC	Any PowerPC (every instruction of every model, the starting choice); 32-bit generic (604e); 750; Gekko (GameCube); Broadway (Wii); 7400 and 7450; 64-bit generic; 970; POWER4 to POWER10; Cell PPE	Both; big-endian is the default	Register names; simplified mnemonics; condition register fields; branch targets

SuperH

CPU	Variants	Byte order	Options
SuperH	SH-1; SH-2 (Saturn, 32X); SH-3; SH-4 (Dreamcast, the starting choice); SH-4A; SH-4 and SH-4A without the FPU	Both; SH-1 and SH-2 big, SH-3 and later little by default	FPSCR.SZ and FPSCR.PR; register 15 name; syntax; PC-relative loads; branch targets

68000 family

CPU	Variants	Byte order	Options
Motorola 68000 family and ColdFire	68000 (the starting choice), 68010, 68020, 68030, 68040, 68060; ColdFire V2, V3, V4	Big-endian	FPU; MMU; syntax (Motorola or GNU MIT); register names; pseudo-instructions

6502 family

CPU	Variants	Byte order	Options
MOS 6502 family	NMOS 6502 (the starting choice); 6510 (Commodore 64); 2A03 (NES, NTSC); 2A07 (NES, PAL); 65C02	Little-endian	None
WDC 65816	65C816; Ricoh 5A22 (Super Nintendo); SA-1	Little-endian	Start in emulation mode; accumulator 8-bit (M); index registers 8-bit (X); follow REP, SEP and XCE
Hudson HuC6280	HuC6280 (PC Engine, TurboGrafx-16)	Little-endian	Follow LDA #, CLA and TAM

Z80 family

CPU	Variants	Byte order	Options
Z80, eZ80, SM83, 8080, 8085	Zilog Z80 (the starting choice); eZ80 in ADL mode (24-bit); eZ80 in Z80 mode (16-bit); Sharp SM83 (Game Boy); Intel 8080; Intel 8085	Little-endian	None (the eZ80 mode is a variant)

Classic 8/16-bit

CPU	Variants	Byte order	Options
Motorola 6809 and Hitachi 6309	MC6809 (the starting choice); HD6309	Big-endian	Direct and extended marks (Motorola or lwasm); direct page register
Motorola 6800, 6801 and Hitachi 6303	MC6800 (the starting choice, also 6802 and 6808); MC6801 (also 6803); HD6303 (also HD6301)	Big-endian	None
RCA CDP1802 COSMAC	CDP1802 (and the A, AC and BC suffix parts)	Big-endian addresses (the chip has 8-bit instructions)	Mnemonic case; register numbers (RA to RF or R10 to R15)
TI TMS9900 and TMS9995	TMS9900 (also 9980A, 9981); TMS9995	Big-endian	Syntax (TI or lower case)

Atmel/TI microcontrollers

CPU	Variants	Byte order	Options
AVR	avr1, avr2, avr25, avr3, avr31, avr35, avr4, avr5 (the starting choice), avr51, avr6, XMEGA, tinyAVR 0/1/2 (avrxt) and the reduced core (avrrc)	Little-endian	Aliases; jump targets in bytes or words; I/O register names of a chosen device
MSP430 and MSP430X	MSP430 (16-bit, the starting choice); MSP430X (20-bit addresses)	Little-endian	Emulated instructions (ret, nop, pop, br)

DEC

CPU	Variants	Byte order	Options
PDP-11	Every instruction of every model (the starting choice); 11/05, 11/10, 11/20; 11/40; 11/45, 11/50, 11/55, 11/70; J-11	Little-endian	Syntax (MACRO-11 or UNIX as); numbers in octal or hexadecimal

Console CPUs

CPU	Variants	Byte order	Options
Toshiba TLCS-900/H (Neo Geo Pocket)	TLCS-900/H	Little-endian	Number syntax ($1F or 1FH); register bank names
Fairchild F8 (Channel F)	F3850 with the 3851, 3852 and 3853 support chips	Big-endian addresses	Mnemonic case
General Instrument CP1610 (Intellivision)	CP1610 (also CP1600)	Big-endian 16-bit words, with 10-bit “decles”; the base address and entry count decles	Mnemonic case; double byte data (SDBD) in force
Signetics 2650 (Arcadia 2001, VC 4000)	2650, 2650A, 2650B	Big-endian addresses	Mnemonic case; register names; number base
NEC V810 (Virtual Boy)	V810	Little-endian	Mnemonic case; register names; condition names; pseudo-instructions

Other

CPU	Variants	Byte order	Options
Xtensa	ESP32 (the starting choice); ESP32-S2; ESP32-S3 with the vector instructions; ESP8266	Both; little-endian is the default (the ESP chips)	Register names; pseudo-instructions; branch targets; L32R operands

Not described

Known, not yet covered

Reference: the Xtensa instruction-set pages are still being written; the overview exists and the table links it.
Viewer: the byte orders shown as “big-endian” for the 6809, 6800, 1802, 9900, F8, 2650 and CP1610 describe how those chips store addresses and words; their decoders have no byte-order option because there is nothing to choose.

Raw Machine Code – The CPU list