HuC6280 Instruction Set

Introduction

The HuC6280 is the processor of the PC Engine (NEC and Hudson Soft, 1987), sold in North America as the TurboGrafx-16, and of the SuperGrafx. Hudson Soft made it: a CMOS 65C02 core with the Rockwell bit instructions (RMB, SMB, BBR, BBS), plus a memory-mapping unit, a timer, an input/output port, an interrupt controller and a six-channel sound generator on the same chip. It runs at two speeds, 1.79 MHz and 7.16 MHz, chosen by the program (CSL and CSH).

It sees 64 KB, as a 65C02 does, but through eight mapping registers, each of which puts any 8 KB of a 2 MB physical space at one eighth of the 64 KB: that is how a game of up to 1 MB fits, and how the hardware registers, the work RAM and the card appear in the same space. See registers, mapping and the memory map.

These pages describe the instruction set as the explorer’s own disassembler reads it. Of the 256 opcodes, 234 are instructions: the 65C02’s (without WAI and STP, which the HuC6280 does not have), and 24 of the HuC6280’s own: the register swaps and clears, the VDC stores, the mapping-register transfers, the block transfers, TST, BSR, the speed selects and SET (the additions). The other 22 opcodes have no instruction (the opcode map).

The pages: registers, flags, mapping registers and the memory map, addressing modes, the 65C02 instructions, what the HuC6280 adds and the opcode map. Each instruction has an anchor, so a disassembled instruction links to its entry. A PC Engine HuCard opens in the explorer with this disassembler: see the .PCE page.

Documented and undefined

The explorer marks each opcode with a status of its own:

There are no instructions that jam the processor, and none whose result varies from chip to chip that the sources read mention.

Notation

The disassembly writes mnemonics in lower case and hexadecimal with a $, in the style of the PC Engine assemblers: lda #$f8, tam #$02, st0 #$05, tst #$01,$20, bbr3 $20,$e010, tii $e000,$2000,$0100. A zero page operand is written with two digits and means an address in $2000-$20FF, an absolute one with four. Every address in a listing is a logical address (16 bits); the physical address behind it depends on the mapping registers, and the viewer shows it when they are known. On the instruction pages each form is written mode opcode, bytes, cycles.

Not described

Known, not yet covered

• Reference: the cycle-by-cycle bus activity, the interrupt latency, how a block transfer is interrupted and resumed, and the timing of the speed change. The pages give total cycle counts.
• Reference: the on-chip peripherals (timer, I/O port, interrupt controller, PSG) beyond their addresses in the memory map.
• Viewer: the disassembler decodes every byte as code: it does not separate code from data and does not follow jumps. It follows lda #n then tam to learn the mapping registers, nothing more.

Unknown

• Reference: what the 22 undefined opcodes do on a real chip, and how long they take (one core takes 2 cycles).
• Reference: the cycle counts of PLA, PLP, PLX, PLY (4 here; the one core read uses 3) and of CSL and CSH (3 here; the core uses 2): the Hudson hardware manual could not be read for this work.
• Reference: whether BIT #immediate sets N and V, and whether TAM and TMA clear the T flag: the one core read says yes to the first and no to the second; no data sheet was read.
• Reference: the result of TMA with more than one bit set in the mask, and of TAM with a mask of 0.

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