HuC6280 Instruction Set – What the HuC6280 adds

Swaps, VDC stores, mapping, block transfers, TST, BSR, speed and the T flag

Introduction

Twenty-four opcodes of the HuC6280 are not in the 65C02. They take the opcodes the 65C02 leaves as no-operations. Each form is written mode opcode, bytes, cycles. Every instruction here clears the T flag when it ends, except SET, which sets it. The opcode bytes of TAI, TAM, TMA, TDD, TIA, TII, TIN, TST, BSR, CLA, ST0, ST1, ST2 and SXY agree with the cc65 assembler’s table; those of SAX, SAY, CLX, CLY, CSL, CSH and SET with a cheat sheet found by search; all with the jspce core.

Swaps and clears

InstructionFormsWhat it doesFlags
sxyimp 02, 1, 3Swap X and Y.none
saximp 22, 1, 3Swap A and X. Not the NMOS 6502’s undocumented SAX (store A AND X).none
sayimp 42, 1, 3Swap A and Y.none
claimp 62, 1, 2A = 0, without changing any flag (unlike lda #0).none
clximp 82, 1, 2X = 0, no flags.none
clyimp C2, 1, 2Y = 0, no flags.none

VDC stores

Three instructions send an immediate byte to the video display controller without a register, an address or a mapping register. The jspce core sends the byte to the VDC directly; what the real chip puts on its address bus was not read.

InstructionFormsWhat it doesFlags
st0imm 03, 2, 4Store the byte in the VDC’s address (register select) port, the one at offset $0000 of the hardware page.none
st1imm 13, 2, 4Store the byte in the VDC data port, low byte (offset $0002).none
st2imm 23, 2, 4Store the byte in the VDC data port, high byte (offset $0003).none

The mapping registers

InstructionFormsWhat it doesFlags
tammask 53, 2, 5Transfer A to every mapping register whose bit is set in the mask (bit 0 is MPR0, bit 7 is MPR7). Use one bit: lda #$F8, tam #$02 sets MPR1. With a mask of 0 the jspce core reuses the previous mask.none
tmamask 43, 2, 4Transfer the mapping register selected by the mask to A. The result with several bits set is not documented.none

Subroutine call, speed and SET

InstructionFormsWhat it doesFlags
bsrrel 44, 2, 8Call a subroutine at a relative target (−128 to +127): push the address of the last byte of the instruction, as JSR does, and branch. Return with RTS.none
cslimp 54, 1, 3Select the low speed, 1.79 MHz.none
cshimp D4, 1, 3Select the high speed, 7.16 MHz.none
setimp F4, 1, 2Set the T flag: the next instruction, if it is ADC, AND, EOR or ORA, works on memory.T

TST

InstructionFormsWhat it doesFlags
tst#,zp 83, 3, 7
#,zp,X A3, 3, 7
#,abs 93, 4, 8
#,abs,X B3, 4, 8		Test memory against an immediate mask without touching A: Z is set when (mask AND memory) is zero; N and V copy bits 7 and 6 of the memory byte. The first operand byte is the mask, the rest the address (zero page at $2000 + n).N V Z

Block transfers

Five instructions copy a block of bytes in one instruction. All are 7 bytes: the opcode, the source address, the destination address and the length, each a 16-bit logical address or count, low byte first. A length of 0 moves 65536 bytes. They take 17 cycles plus 6 for each byte moved, and the processor can be interrupted between two bytes. The instruction saves A, X and Y and puts them back when it ends (the Hudson manual says it uses them to count, through a search summary; the jspce core leaves them untouched and the explorer lists no register as changed). No flag changes.

InstructionFormsWhat it doesFlags
tiisrc,dst,len 73, 7, 17 + 6nSource goes up, destination goes up: memory to memory.none
tddsrc,dst,len C3, 7, 17 + 6nSource goes down, destination goes down: copies from the end of the block, so overlapping blocks can be moved up.none
tinsrc,dst,len D3, 7, 17 + 6nSource goes up, destination stays: the destination is a port (the VDC data port, a PSG register).none
tiasrc,dst,len E3, 7, 17 + 6nSource goes up, destination alternates: destination, destination + 1, destination, destination + 1 …; feeds the two VDC data ports from memory.none
taisrc,dst,len F3, 7, 17 + 6nSource alternates: source, source + 1, source, source + 1 …; destination goes up.none

The T flag

The T flag changes what ADC, AND, EOR and ORA do for one instruction. With T clear they work on A as always. set sets T; the very next instruction, if it is one of these four, then does the following (checked on the jspce core):

  • the byte it would combine with A (its operand, in any addressing mode) is combined with the byte at zero page address X, that is $2000 + X, instead of A;
  • the result is written back to that byte, not to A; A is not changed;
  • N, Z (and V, C for ADC) are set from the result;
  • it takes 3 more cycles.

So set then adc #$01 adds one to the byte at $2000 + X: the zero page acts as a bank of 256 accumulators, indexed by X. SBC is not affected. Every instruction clears T when it ends, except SET, so the effect lasts for one instruction only; if that instruction is not one of the four, T is simply cleared. An interrupt between SET and the instruction is the program’s problem. A disassembler cannot know whether T is set, so the explorer marks ADC, AND, EOR and ORA with a note.

The jspce core does not clear T for TAM and TMA; the explorer says every instruction but SET does. PLP and RTI load T from the stack with the other flags.

Not described

Known, not yet covered

  • Reference: how a block transfer is interrupted and resumed, and what the saved registers do to the stack.
  • Reference: the VDC registers that ST0, ST1 and ST2 write, and the PSG registers TIN is used on.

Unknown

  • Reference: whether an interrupt can occur between SET and the next instruction; whether ST0-ST2 go through the mapping registers on real hardware; the cycles of CSL and CSH (3 here, the core reads 2).

Links

Reference