6502 Instruction Set

Introduction

The MOS Technology 6502, released in 1975, is an 8-bit processor with a 16-bit address bus: 64 KB of memory. It has three 8-bit registers (the accumulator A and the index registers X and Y), an 8-bit stack pointer S, a 16-bit program counter and a status register P. The stack is fixed in page one, $0100–$01FF. It ran the Apple II, the Commodore PET, the Atari 8-bit computers, the BBC Micro, the Atari VCS (as the 6507) and, as the 6510, the Commodore 64.

These pages describe the instruction set as the explorer’s own disassembler reads it: every opcode of the NMOS 6502, the undocumented ones too, and the 65C02’s changes. Each instruction has an anchor, so that a disassembled instruction links to its entry.

The pages: addressing modes, the instructions in four groups (data transfer, arithmetic, logic and shifts, control transfer), the flag instructions and NOP, and the opcode map of all 256 opcodes.

A file of 6502 code opens in the explorer when its format is known; the first is the Commodore 64 .PRG program. The disassembly has an instruction decoded at every byte, laid out in columns so that code reached by a jump into the middle of another instruction can be read. The processor is chosen in the options bar above the viewer.

Registers and flags

Register	Size	What it holds
`A`	8 bits	The accumulator: the target of most arithmetic and logic.
`X`, `Y`	8 bits	Index registers, added to an address by the indexed modes, and counters.
`S`	8 bits	The stack pointer: the low byte of the next free stack address in page one. It counts down as bytes are pushed.
`PC`	16 bits	The program counter.
`P`	8 bits	The status register, below.

The status register P, from bit 7 to bit 0 (the instruction pages give the flags each instruction changes):

Bit	Flag	Name	Meaning
7	`N`	Negative	A copy of bit 7 of the last result.
6	`V`	Overflow	Signed overflow of ADC and SBC; BIT copies bit 6 of the memory byte into it.
5	–	Unused	Always 1 when P is pushed on the stack.
4	`B`	Break	Not a flag in the register: it exists only in the copy of P pushed on the stack, 1 when pushed by BRK or PHP and 0 when pushed by an interrupt.
3	`D`	Decimal	When set, ADC and SBC work in binary-coded decimal (not on the 2A03).
2	`I`	Interrupt disable	When set, the IRQ is ignored; the NMI is not.
1	`Z`	Zero	Set when the last result was zero.
0	`C`	Carry	The carry out of the last addition or shift; the inverse of the borrow in subtraction and comparison.

The family

The explorer decodes these chips; the options bar picks one. The decode is the same for the first three.

Chip	Where	What differs
NMOS 6502	Apple II, PET, Atari 8-bit, BBC Micro, Atari VCS (6507)	All 256 opcodes decode: 151 documented, the rest undocumented.
6510	Commodore 64	The same decode as the NMOS 6502. It adds an 8-bit I/O port mapped at addresses 0 and 1, which the C64 uses to switch ROM and RAM in and out.
2A03 and 2A07	Nintendo Entertainment System (NTSC and PAL)	The same decode as the NMOS 6502, with the decimal mode removed: SED and CLD still set and clear the D flag, but ADC and SBC always work in binary. The chip also holds the sound generator and the sprite DMA.
65C02	Apple IIc and IIe enhanced, later BBC Masters, many embedded systems (WDC W65C02S)	New instructions and addressing modes; every opcode is defined, with no undocumented ones. 65C02 additions lists them. The Rockwell and WDC bit instructions (RMB, SMB, BBR, BBS) are included.

The 65816 and the HuC6280 are related but not yet decoded.

Documented, undocumented, unstable

Every instruction the explorer decodes has a status, shown in the disassembly with its own highlight and the status in words:

Status	Meaning
Documented	In the data sheet for the chip.
Undocumented	Not in the data sheet, but it does the same on every chip of the family.
Unstable	Not in the data sheet, and the result differs between chips, revisions or conditions. Do not rely on it.
Jam	Stops the processor until it is reset.

On the NMOS 6502 and its relatives there are 151 documented opcodes, 85 stable undocumented ones, 8 unstable ones and 12 that jam: 256 in all. The status depends on the chip chosen: the 65C02 defines all 256 opcodes, so none is undocumented there.

Notation

The disassembly writes mnemonics in lower case and hexadecimal with a $: lda #$01, sta $d020, lda ($fb),y, jmp ($0314). # marks an immediate value; a branch is shown with its target address, not the signed offset in the file. Cycle counts are the base count; “+1 page” means one more when the index addition crosses a page boundary.

Not described

Known, not yet covered

Reference and viewer: the 65816 (the Super NES and Apple IIGS chip) and the HuC6280 (the PC Engine chip). They extend the 6502 and are documented; the decoder has a place for them but they are not built.
Reference: the cycle-by-cycle bus activity of each instruction (the dummy reads and writes), which matters to cycle-exact emulation. The pages give only total cycle counts.

Unknown

Reference: the exact result of the unstable opcodes on each chip revision. The pages say what they do in the usual case and that it varies.