Introduction
Seven instructions set or clear one flag of the status register, each one byte and 2 cycles. The other flags (N, Z and V) are set only by the instructions that compute them, and V can be cleared but not set directly. The flags are described on the overview.
The instructions
| Instruction | Opcode | What it does | Flags |
|---|---|---|---|
clc | 18 | Clears the carry. Done before an addition (ADC). | C |
sec | 38 | Sets the carry. Done before a subtraction (SBC). | C |
cli | 58 | Clears the interrupt-disable flag: IRQ interrupts are taken. | I |
sei | 78 | Sets the interrupt-disable flag: IRQ interrupts are ignored (the NMI is not). | I |
cld | D8 | Clears the decimal flag: ADC and SBC work in binary. | D |
sed | F8 | Sets the decimal flag: ADC and SBC work in decimal. On the NES’s 2A03 the flag is set but has no effect. | D |
clv | B8 | Clears the overflow flag. There is no “set overflow” instruction; the chip’s SO pin can set it, and ADC, SBC and BIT can. | V |
nop | EA | Does nothing for 2 cycles. It is the only documented NOP; the chip has many more opcodes that do nothing, of 1 to 3 bytes, which are undocumented. | – |
Notes
- Code that must not be interrupted by an IRQ starts with SEI and ends with CLI, or with PLP of a P it saved with PHP.
- The 65C02 defines the NOPs that were undocumented on the NMOS chip, of the same sizes (1, 2 and 3 bytes), so a 65C02 decode shows them as documented.