6502 Instruction Set: 65C02 additions

Introduction

The 65C02 is a CMOS redesign of the 6502 with the same registers and the same documented instructions, plus new instructions, new addressing modes for old ones, and fixes for the NMOS chip’s quirks. It ran the Apple IIc and the enhanced Apple IIe, and later versions are still made by Western Design Center (the W65C02S). Every one of its 256 opcodes is defined; none is undocumented, so the explorer shows all of them as documented when it decodes for the 65C02.

The bit instructions (RMB, SMB, BBR, BBS) came from Rockwell’s R65C02, and WAI and STP from WDC; the W65C02S has all of them, and that is the set the explorer decodes. Some other 65C02-family chips lack some of them (the 65SC02 has no bit instructions, for example).

New instructions

Instruction	Forms	What it does	Flags
`bra`	rel `80`, 2, 3 +1 page	Branches always, over the usual signed 8-bit displacement.	–
`stz`	zp `64`, 2, 3 zp,X `74`, 2, 4 abs `9C`, 3, 4 abs,X `9E`, 3, 5	Stores zero.	–
`phx`	`DA`, 1, 3	Pushes X.	–
`phy`	`5A`, 1, 3	Pushes Y.	–
`plx`	`FA`, 1, 4	Pulls X.	N Z
`ply`	`7A`, 1, 4	Pulls Y.	N Z
`tsb`	zp `04`, 2, 5 abs `0C`, 3, 6	Test and set bits: Z is set when A AND memory is zero (as BIT does), then the memory byte becomes memory OR A.	Z
`trb`	zp `14`, 2, 5 abs `1C`, 3, 6	Test and reset bits: Z as for TSB, then the memory byte becomes memory AND (NOT A).	Z
`inc a`	`1A`, 1, 2	Adds one to the accumulator.	N Z
`dec a`	`3A`, 1, 2	Subtracts one from the accumulator.	N Z
`wai`	`CB`, 1, 3	Waits for an interrupt: the processor stops until an interrupt (or reset). With I set, an IRQ simply resumes the program after WAI without taking the interrupt.	–
`stp`	`DB`, 1, 3	Stops the processor until it is reset.	–

New modes for old instructions

Instruction	New forms
ORA, AND, EOR, ADC, STA, LDA, CMP, SBC	(zp) zero page indirect: `12 32 52 72 92 B2 D2 F2` in that order, 2 bytes, 5 cycles.
`jmp`	(abs,X) `7C`, 3 bytes, 6 cycles: a jump table.
`bit`	imm `89` (2, 2), zp,X `34` (2, 4), abs,X `3C` (3, 4 +1 page). The immediate form sets only Z; N and V are untouched.

The bit instructions (Rockwell and WDC)

Each exists for the eight bit numbers 0 to 7. The opcode encodes the bit in its high nibble, so 07 is RMB0, 17 RMB1 and so on up to 77.

Instruction	Opcodes	What it does
`rmb0`–`rmb7`	`07 17 27 37 47 57 67 77`, zp, 2 bytes, 5 cycles	Resets (clears) one bit of a zero-page byte. No flags change.
`smb0`–`smb7`	`87 97 A7 B7 C7 D7 E7 F7`, zp, 2 bytes, 5 cycles	Sets one bit of a zero-page byte. No flags change.
`bbr0`–`bbr7`	`0F 1F 2F 3F 4F 5F 6F 7F`, zp and relative, 3 bytes, 5 cycles	Branches if the bit of the zero-page byte is reset (0). The operands are the zero-page address and then the branch displacement, counted from the end of the 3-byte instruction.
`bbs0`–`bbs7`	`8F 9F AF BF CF DF EF FF`, zp and relative, 3 bytes, 5 cycles	Branches if the bit of the zero-page byte is set (1).

On the NMOS 6502 these opcodes are undocumented: the x7 opcodes are the read-modify-write combinations SLO, RLA, SRE, RRA, SAX, LAX, DCP and ISC, and the xF opcodes their absolute forms.

Changed behaviour

JMP (indirect) reads its pointer across a page boundary correctly (the NMOS bug of wrapping within the page is fixed) and takes 6 cycles, not 5.
Decimal mode. ADC and SBC in decimal mode set N, V and Z from the decimal result and take one more cycle.
Interrupts and BRK clear the D flag as they take the interrupt.
Shifts and rotates with absolute,X take 6 cycles (+1 page), not 7. INC and DEC with absolute,X still take 7.
Read-modify-write. The chip reads the byte twice, not read then write the old value, which matters on hardware registers.

The defined NOPs

Every NMOS opcode that is undocumented and that the 65C02 does not give a new instruction is a NOP, of a fixed size, so the processor never jams on an opcode. They are documented on this chip.

Opcodes	Bytes	Cycles
`x3` and `xB` except `CB` (WAI) and `DB` (STP): `03 13 23 33 43 53 63 73 83 93 A3 B3 C3 D3 E3 F3 0B 1B 2B 3B 4B 5B 6B 7B 8B 9B AB BB EB FB`	1	1
`02 22 42 62 82 C2 E2`	2	2
`44`	2	3
`54 D4 F4`	2	4
`5C`	3	8
`DC FC`	3	4

6502 Instruction Set – 65C02 additions