Introduction
All of the 65C02’s addressing modes are there, and a few more. Every address an instruction names is a logical address: the mapping registers (see the mapping registers) turn it into a physical one afterwards. The one place where the HuC6280 differs from the 65C02 in the modes themselves is the zero page.
The zero page is at $2000
A zero page operand zp is a byte n; the address it names is $2000 + n, not n. The stack is the next
page, $2100-$21FF. Both are logical addresses: with MPR1 = $F8 they are the first 512 bytes of the work RAM. A disassembly writes
only the byte (lda $05), and the viewer shows the full address, $2005, as the reference.
Indexed zero page modes wrap inside the page: lda $ff,x with X = 2 reads $2001.
The modes
The cycle counts here are the base counts of the instruction (the instruction pages give each opcode’s own); a taken branch, the T flag and decimal mode add cycles, see cycles.
| Mode | Written | Bytes | The operand is |
|---|---|---|---|
| Implied | clc | 1 | nothing: the instruction names its registers. |
| Accumulator | asl a | 1 | A. |
| Immediate | lda #$12 | 2 | the byte after the opcode. |
| Zero page | lda $12 | 2 | the byte at $2000 + $12. |
| Zero page,X | lda $12,x | 2 | the byte at $2000 + (($12 + X) AND $FF). |
| Zero page,Y | ldx $12,y | 2 | the same with Y; only LDX and STX have it. |
| Absolute | lda $4000 | 3 | the byte at the 16-bit logical address. |
| Absolute,X | lda $4000,x | 3 | the address plus X. |
| Absolute,Y | lda $4000,y | 3 | the address plus Y. |
| (Zero page) | lda ($12) | 2 | the byte at the address held in the two zero page bytes $12 and $13 (the 65C02 mode). |
| (Zero page,X) | lda ($12,x) | 2 | the byte at the address held at zero page $12 + X. |
| (Zero page),Y | lda ($12),y | 2 | the byte at the address held at zero page $12, plus Y. |
| Absolute indirect | jmp ($4000) | 3 | JMP only: the address held at $4000. |
| Absolute indirect,X | jmp ($4000,x) | 3 | JMP only: the address held at $4000 + X. |
| Relative | bne $e010 | 2 | a target within −128 to +127 bytes of the next instruction (also BRA and BSR). The disassembly writes the target. |
| Zero page and relative | bbr3 $12,$e010 | 3 | BBR and BBS: the zero page byte tested, then the branch offset, counted from the next instruction. |
| Immediate mask | tam #$02 | 2 | TAM and TMA: a byte with one bit for each mapping register. |
| Immediate, then memory | tst #$01,$12tst #$01,$12,xtst #$01,$4000tst #$01,$4000,x | 3, 3, 4, 4 | TST only: an immediate mask, then a zero page or absolute address (indexed by X or not). See TST. |
| Block | tii $e000,$2000,$0100 | 7 | The five block transfers: source address, destination address, length, three 16-bit words, low byte first. See block transfers. |
The longest instruction is 7 bytes, so in the viewer’s columns an instruction that starts inside another can be up to seven columns away.
Cycles
The cycle counts are CPU cycles. The base counts, by mode, of the instructions that read memory (ADC, AND, CMP, EOR, LDA, ORA, SBC, and BIT, LDX, LDY, CPX, CPY where the mode exists): immediate 2, zero page 4, zero page indexed 4, absolute 5, absolute indexed 5, (zero page) 7, (zero page,X) 7, (zero page),Y 7. Stores (STA, STX, STY, STZ) take the same count as the load with that mode. Shifts, rotates, INC and DEC take 2 on A, 6 on zero page, 6 on zero page,X, 7 on absolute and 7 on absolute,X. What can be added:
- Taken branch: +2 (a branch not taken takes 2; BBR and BBS 6 and 8; BRA always 4; BSR 8).
- T flag set: ADC, AND, EOR, ORA +3.
- Decimal mode (D set): ADC and SBC +1.
- Block transfers: 17 + 6 for each byte moved.
There is no page-crossing cycle: an indexed access takes the same time wherever it lands. These counts come from the jspce core’s cycle table and the Hudson table as remembered; a few differ between them (the overview lists which). The speed the processor runs at, 1.79 or 7.16 MHz, decides how long a cycle lasts, not how many there are.
Not described
Known, not yet covered
- Reference: the extra cycle or cycles of a page-crossing access, if any, and of the bus waits when the processor reads the slow VDC or the CD-ROM interface.
Unknown
- Reference: where the high byte of a (zero page) pointer at $FF comes from: the jspce core reads it from $2100 (the stack page) without wrapping; no data sheet was read that says so.
Links
Reference
- CPU memory map – the zero page and the stack at $2000 and $2100
- jspce – the core whose cycle table the counts were checked against