HuC6280 Instruction Set – Registers, mapping and memory map

Introduction

The programmer’s registers are those of the 65C02: the accumulator A, the index registers X and Y, the stack pointer S, the program counter and the status register P, all 8 bits except the 16-bit program counter. What is new is the T flag in P and the eight mapping registers, which stand between the 16-bit addresses a program uses and the 21 address lines of the chip.

The registers

The status register

The bit positions are those the jspce core uses (T at bit 5, which is the 65C02’s unused bit); the Hudson manual that would state them could not be read.

The mapping registers

The 16-bit logical address space is cut into eight segments of 8 KB. The top three bits of an address choose the mapping register for the segment, and the register’s 8 bits become the top 8 bits of a 21-bit physical address; the low 13 bits pass through:

physical = MPRn × $2000 + (logical AND $1FFF), with n = the top three bits of the logical address.

Example: with MPR1 = $F8, logical $2005 (zero page address $05) is physical $F8 × $2000 + $0005 = $1F0005, in the work RAM. The program sets a register with TAM: lda #$F8 then tam #$02 (mask $02 selects MPR1). TMA reads one back into A.

At reset the reset vector is read from logical $FFFE, and the sources read put it at physical $001FFE, the last two bytes of the first 8 KB of the HuCard; so MPR7 must be $00 at reset. The sources read do not say what the other registers hold at reset, so they are not known here; a program sets them before it uses them. Programs and the system software usually set MPR0 to $FF (the hardware page) and MPR1 to $F8 (the work RAM).

The explorer’s decoder takes the registers as eight options. Its defaults are the usual setup (MPR0 = $FF, MPR1 = $F8, MPR7 = $00, the others not known), and it learns the rest from a lda #n (or cla) directly followed by a tam in the code it is reading.

The physical memory map

The value in a mapping register is a bank number; the physical space has 256 banks of 8 KB (2 MB).

Zero page and stack are at fixed logical addresses, $2000-$20FF and $2100-$21FF; where they land physically depends on MPR1, and a program that maps something else at $2000-$3FFF moves them.

The hardware page (bank $FF)

With MPR0 = $FF the registers are at the start of the logical space. Each block is mirrored through its 1 KB.

The SuperGrafx puts two VDCs and a priority controller (VPC) at $0000-$001F instead. ST0, ST1 and ST2 write the VDC directly.

Interrupt vectors

The vectors are at the top of the logical space, so they come from whatever bank MPR7 maps at $E000-$FFFF (on a HuCard, its last 8 KB).

Unlike the 65C02, BRK does not go through $FFFE (here the reset vector) but through $FFF6, shared with IRQ2. Each vector is a 16-bit address, low byte first.

Not described

Known, not yet covered

• Reference: the registers of the VDC, VCE, PSG, timer, I/O port and interrupt controller (only their address blocks are listed).
• Reference: the banks used by the CD-ROM system, the Super System Card and the Arcade Card, and the Street Fighter II mapper.

Unknown

• Reference: the value of MPR0-MPR6 at reset, and the exact bit position of T in a pushed status byte on real hardware.

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