TMS9900 Instruction Set

Introduction

The TMS9900 is a 16-bit processor Texas Instruments introduced in 1976, the processor of the TI-99/4A home computer (1981) and of the TI-990 minicomputer family it was derived from. It has no general-purpose registers on the chip: the sixteen registers R0 to R15 are sixteen words of ordinary memory, found through a workspace pointer register, and a context switch is a change of that pointer. It is big-endian, addresses 64 KB in bytes, and every instruction is one, two or three 16-bit words, always at an even address.

These pages describe the instruction set as the explorer’s own disassembler reads it. There are 69 instructions in the TMS9900 (and the TMS9980A and 9981, which have the same set), laid out in nine formats; the TMS9995 adds four more (DIVS, MPYS, LST and LWP). Words that no instruction uses are illegal opcodes.

The pages: registers, status register and vectors, addressing modes and the nine formats, every instruction and the opcode map with the illegal words. Each instruction has an anchor, so a disassembled instruction links to its entry.

Statuses in the disassembly

Status	Meaning
Documented	One of the 69 instructions of the TMS9900 (or, for the TMS9995 variant, of its 73), with its unused bits zero.
Undocumented	An instruction whose unused bits are not zero: bits 11 to 15 of the no-operand instructions (IDLE, RSET, RTWP, CKON, CKOF, LREX: 32 words each) and bit 11 of the immediate instructions (LI, AI, ANDI, ORI, CI, STWP, STST, LWPI, LIMI). The data manual calls the bits unused; a real chip may or may not decode them. The one core read for this work (js99er) treats them as illegal. 330 words.
Not in this ISA	An instruction of the TMS9995 decoded as TMS9900.
Illegal	A word no instruction uses (1,696 words on the TMS9900). What a real chip does is not documented in the sources read.
Odd address	A byte at an odd address. An instruction cannot start there: the processor ignores the low address bit. The listing decodes at every byte, so these show as one-byte entries.

Notation

The disassembly follows the Texas Instruments assembler by default: upper-case mnemonics, hexadecimal with a leading >, registers R0 to R15, the operand forms R1, *R1, *R1+, @>8300 and @>8300(R1): MOV @>8300(R2),*R3+, LI R1,>1234, JNE >6012, SBO 5. A jump shows the address it goes to (an assembler writes $+4 or a label). The plain syntax option writes lower case and $ hexadecimal like the other decoders on this site. An operand is the source first and the destination second, as in MOV source,destination. NOP (JMP $+2, word >1000) and RT (B *R11, >045B) are assembler names for words that decode as the instruction shown, and appear as the alias.

Not described

Known, not yet covered

Reference: clock cycles and memory accesses per instruction, and the wait states of the TI-99/4A’s 8-bit bus: no readable source was found for this work, so the pages give none.
Reference: the TI-990 models’ own additions (the 990/10, 990/10A and 990/12 have up to 144 instructions: string, floating point, memory map), the TMS99105A and TMS99110A extensions, the TMS9995’s on-chip RAM and its illegal-opcode interrupt, the CRU hardware and the interrupt levels beyond their vectors.
Reference: the TI-99/4A cartridge, GROM and disk formats that carry TMS9900 code are separate pages (not written yet).
Viewer: the disassembler decodes every even address as an instruction; it does not separate code from data and does not follow workspace changes. There is no viewer for a file format yet that uses it.

Unknown

Reference: what a real chip does with the 1,696 illegal words, and with the 330 words that set an unused bit.
Reference: the TMS9995 additions (DIVS, MPYS, LST, LWP) rest on a recollection of the data manual and a Wikipedia list that gives only mnemonics; no core on this Mac implements them.
Reference: which side effects of X (execute), of the dummy read that MOV makes of its destination and of STCR’s fill bits real chips have: the sources read were summaries.