Introduction
An instruction is a 16-bit word, so the map is indexed by the high byte: the row is the high nibble, the column the next one, and a cell lists the instructions found in the 256 words of that high byte (the low byte holds the operand fields). A dash means that some words of the cell are illegal. Cells marked as illegal are entirely so. The map is for the TMS9900; the TMS9995’s four extra instructions are listed below it. Instructions with unused bits set (the Undocumented status) are inside the cells of their instruction and not marked separately.
The map
| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x | - | - | LI AI ANDI ORI CI STWP STST LWPI | LIMI - IDLE RSET RTWP CKON CKOF LREX | BLWP B X CLR | NEG INV INC INCT | DEC DECT BL SWPB | SETO ABS - | SRA | SRL | SLA | SRC | - | - | - | - |
| 1x | JMP | JLT | JLE | JEQ | JHE | JGT | JNE | JNC | JOC | JNO | JL | JH | JOP | SBO | SBZ | TB |
| 2x | COC | COC | COC | COC | CZC | CZC | CZC | CZC | XOR | XOR | XOR | XOR | XOP | XOP | XOP | XOP |
| 3x | LDCR | LDCR | LDCR | LDCR | STCR | STCR | STCR | STCR | MPY | MPY | MPY | MPY | DIV | DIV | DIV | DIV |
| 4x | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC | SZC |
| 5x | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB | SZCB |
| 6x | S | S | S | S | S | S | S | S | S | S | S | S | S | S | S | S |
| 7x | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB | SB |
| 8x | C | C | C | C | C | C | C | C | C | C | C | C | C | C | C | C |
| 9x | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB | CB |
| Ax | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A |
| Bx | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB | AB |
| Cx | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV | MOV |
| Dx | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB | MOVB |
| Ex | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC | SOC |
| Fx | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB | SOCB |
Illegal words
The TMS9900 data manual (as quoted by the opcode table read for this work) leaves four ranges of words without an instruction. They are
1,696 words in all; the explorer shows each as a two-byte DATA word with the status Illegal.
| Range | Words | Note |
|---|---|---|
>0000 to >01FF | 512 | The TMS9995 defines DIVS (>0180 to >01BF), MPYS (>01C0 to >01FF), LST (>0080 to >008F) and LWP (>0090 to >009F) here; the TI-990 models use other words here. |
>0320 to >033F | 32 | Between LIMI and IDLE. The TI-990 models with a memory map have an LMF instruction (load memory map file); its opcode was not read for this work. |
>0780 to >07FF | 128 | After ABS. Some TI-990 models define instructions here. |
>0C00 to >0FFF | 1024 | After the shifts. js99er’s F18A graphics processor (a TI-99/4A video chip with its own CPU) uses part of this range for its own instructions; they are not TMS9900 instructions. |
What a real TMS9900 does with an illegal word is not documented in the sources read. The explorer shows it as one word with no operands. The TMS9995 has an illegal-opcode interrupt; the TMS9900 is not known to trap.
TMS9995 additions
| Range | Instruction |
|---|---|
>0080 to >008F | LST |
>0090 to >009F | LWP |
>0180 to >01BF | DIVS |
>01C0 to >01FF | MPYS |
Not described
Known, not yet covered
- Reference: the words of the TI-990 models’ extra instructions (990/10, 990/10A, 990/12 and the TMS99105A and TMS99110A), most of which lie in the illegal ranges above.
Unknown
- Reference: the behaviour of the illegal words on real chips, and the exact range of words the TMS9995 uses for its four additions (one low-byte alignment is assumed: the instruction occupies the whole range given).