TMS9900 Instruction Set – Instructions

Introduction

Each row gives the instruction, the base opcode (the word with every operand field zero), its format, what it does and the status bits it changes (L> A> EQ C OV OP X and the interrupt mask IM; see the status register). Source and destination are general operands. Operands are written source first, as in the TI assembler. Clock cycles are not given: no readable source was found (see the overview). The word counts: format I 1 to 3, formats III, IV, VI, IX 1 to 2, format VIII 1 to 2, the rest 1.

Two general operands (format I)

Bit 12 of the word makes the byte form (the name ends in B). A byte operand in a register is its high byte. The destination of every instruction except C and CB is changed (MOV does not read it as data, the others combine it with the source). MOV and MOVB read the destination before writing it; this matters only when the destination is a hardware address.

Jumps (format II)

Target = address of the jump + 2 + 2 × the signed displacement (−128 to +127 words). The assembler name NOP is the jump with displacement 0 (>1000); a displacement of −1 (>10FF) jumps to itself. The conditions: arithmetic compares use A>, logical compares L>.

CRU instructions (formats II and IV)

The CRU (communications register unit) is a serial bit-addressed I/O space of 4096 bits. The base is R12 / 2; SBO, SBZ and TB add the signed displacement to it. LDCR and STCR transfer 1 to 16 bits starting at the base bit: a count C of 1 to 8 uses a byte operand, 9 to 15 and 0 (meaning 16) a word operand.

Register and general operand (format III)

Extended operation, multiply and divide (format IX)

Shifts (format V)

The count is in the word (1 to 15); a count of 0 takes the count from the low four bits of R0, where 0 means 16.

One general operand (format VI)

No operand (format VII)

The five external instructions put a code on the address bus (for hardware that watches it) and do nothing else on the chip; assemblers write the five unused low bits as zero.

Immediate and register (format VIII)

All but STWP and STST are followed by a 16-bit immediate word.

TMS9995 additions

Decoded only when the TMS9995 variant is chosen; on the TMS9900 the words are Not in this ISA. These four rest on a recollection of the TMS9995 data manual and a list of mnemonics by model (Wikipedia); no core or readable table was available, so the opcodes and flags are unconfirmed.

Not described

Known, not yet covered

• Reference: clock cycles, memory accesses and wait states of each instruction.
• Reference: the exact flag results of the arithmetic instructions at the edges (NEG of >8000, ABS of >8000, SLA by 16) are described only in words.

Unknown

• Reference: the status flags of the TMS9995 additions; the C flag of ABS (the one core read always clears C for it; the table read lists C as changed).
• Reference: the flags published for SOCB and SRL in one table disagree with the other sources (it lists C for SOCB and OV for SRL); this page follows the data manual as remembered and the core.

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