Introduction
The processor itself holds only three 16-bit registers: the program counter (PC), the
workspace pointer (WP) and the status register (ST). Everything else a program calls a
register, R0 to R15, is a word of memory: register n is the word at address WP + 2n. Changing WP
changes all sixteen registers at once, which is how a subroutine call (BLWP) and an interrupt save and restore a whole
register set without copying it. The consequence for a disassembler: a register operand is a register, but the address it
stands for needs the current WP, so the explorer reports register operands as registers and notes only the address
form (WP+2n).
The registers
| Register | Notes |
|---|---|
PC | The address of the next instruction. Always even (the low bit is ignored). |
WP | The address of R0. Even. Set by LWPI, by the context switches BLWP, XOP, RTWP and by interrupts and reset; read by STWP. |
ST | The status register: see below. Read by STST, set by LIMI (the mask only) and RTWP. |
R0 | An ordinary register, and the shift count source when an instruction’s count is 0 (the low four bits of R0). It cannot be an index register: @addr(R0) is the symbolic form. |
R1 to R10 | General purpose. |
R11 | BL puts the return address here (the return is B *R11, assembler name RT). XOP puts the operand address in the new R11. |
R12 | The CRU base address (bits 3 to 14 are used: the bit address is R12 / 2). SBO, SBZ, TB, LDCR and STCR add to it. |
R13, R14, R15 | The saved WP, PC and ST of the old context after BLWP, XOP or an interrupt. RTWP restores WP, PC and ST from them. |
A byte instruction on a register uses the high (even-addressed) byte of the register word, because the machine is big-endian.
The status register
The bits are numbered from the most significant bit as bit 0, as Texas Instruments does; the column on the right is the value as a word.
| Bit | Name | Meaning | Mask |
|---|---|---|---|
| 0 | L> | Logical greater than: the result as an unsigned number is above zero (for compares: the first operand is above the second, unsigned). | >8000 |
| 1 | A> | Arithmetic greater than: the result as a signed number is above zero (for compares: signed). | >4000 |
| 2 | EQ | Equal: the result is zero (for compares: the operands are equal; for COC, CZC and TB: the test passed). | >2000 |
| 3 | C | Carry out of the most significant bit (for subtraction the carry means no borrow; for shifts the last bit shifted out). | >1000 |
| 4 | OV | Overflow: the signed result does not fit. DIV sets it when the quotient does not fit. | >0800 |
| 5 | OP | Odd parity: the number of one bits in the result byte is odd. Set only by byte instructions (and by LDCR/STCR with a byte count). | >0400 |
| 6 | X | Set when an XOP is taken. | >0200 |
| 7 to 11 | Not used. | >01F0 | |
| 12 to 15 | mask | The interrupt mask: an interrupt of level n is accepted when n is not above the mask. LIMI loads it; an interrupt sets it to one less than its own level. | >000F |
Every conditional jump reads some of the bits L> A> EQ C OV OP: see the jumps.
The context switch
A transfer vector is two consecutive words in memory: the new workspace pointer, then the new program counter. BLWP takes its vector from the operand address; XOP from >0040 + 4 × the XOP number; an interrupt of level n from 4 × n; reset from address 0. In each case the old WP, PC and ST are stored in R13, R14 and R15 of the new workspace; XOP also stores the address of its operand in the new R11 and sets the X bit. RTWP undoes it: R13 to WP, R14 to PC, R15 to ST.
The vectors
| Address | Used by |
|---|---|
>0000 and >0002 | Reset (level 0): the workspace pointer, then the program counter. |
>0004 to >003C | Interrupt levels 1 to 15 (four bytes each). Level 2 is the TI-99/4A’s VDP interrupt, in the console ROM at >0004. |
>0040 to >007C | XOP 0 to 15 (four bytes each). The TI-99/4A’s console ROM puts its own workspaces and entry points there. |
>FFFC and >FFFE | Non-maskable interrupt (the LOAD signal). |
The machine-specific part (the TI-99/4A’s 256 bytes of fast RAM at >8300, the memory-mapped video and sound ports, GROM access) is the business of the TI-99/4A pages, not of the processor.
Not described
Known, not yet covered
- Reference: the interrupt acceptance sequence in detail, the CRU address decoding, and the TMS9995’s internal 256-byte RAM at >F000 and its different interrupt and reset sequence.
- Reference: the TI-99/4A memory map and the cartridge, GROM and disk formats.
Unknown
- Reference: the exact state of the status register after reset and which of its unused bits read as one on real chips.
- Reference: whether the NMI vector at >FFFC is present on every TMS99xx part (the page rests on the data manual as remembered; the scan could not be read).
Links
Reference
- TI-990 – Wikipedia: the architecture and the status register
- Editor/Assembler manual – the TI-99/4A manual: the status register bits and transfer vectors (section 3)