TMS9900 Addressing Modes and Formats

Introduction

An instruction word is divided into bit fields. Bits are numbered here from the least significant bit (bit 0) of the word as the decoder does; Texas Instruments numbers from the left. A general operand is a six-bit field: a two-bit mode T (bits 5 and 4 for the source, bits 11 and 10 for the destination) and a four-bit register number (bits 3 to 0, or 9 to 6).

The five modes

T	Mode	Assembler form	The operand is	Extra word
0	Workspace register	`R5`	the register itself (the word at WP + 2 × 5)	no
1	Register indirect	`*R5`	the memory at the address held in R5	no
2, register 0	Symbolic	`@>8300`	the memory at the address in the next word	yes
2, register 1 to 15	Indexed	`@>8300(R5)`	the memory at the next word plus R5	yes
3	Register indirect, auto-increment	`*R5+`	the memory at the address in R5; afterwards R5 is increased by 1 for a byte instruction and 2 for a word instruction	no

R0 cannot be an index register: T = 2 with register 0 is the symbolic mode. Extension words follow the instruction word in order: the source operand’s word, then the destination operand’s. A two-operand instruction is therefore one to three words (2, 4 or 6 bytes).

The effective address is a memory address, so the explorer reports it only when it does not depend on a register: a symbolic operand’s address is shown as refers; an indexed operand shows its base word and the index register. Memory accesses are always to an even address (the low bit of a word address is ignored); a byte instruction uses the low bit to pick the byte.

Alignment

Instructions start at even addresses: the processor drops the low bit of the program counter. When a listing decodes at every byte the bytes at odd addresses are not the start of any instruction; the explorer shows each as a one-byte entry with the status Odd address. A word is read big-endian: the first byte at the even address is the high byte.

The nine formats

Fields are listed from the most significant bit. Ts and S are the source mode and register, Td and D the destination’s; B is 1 for a byte instruction.

Format	Fields	Words	Instructions
I	opcode (3 bits) B Td D Ts S	1 to 3	A AB C CB MOV MOVB S SB SOC SOCB SZC SZCB
II	opcode (8 bits) displacement (8 bits, signed)	1	JMP and 12 conditional jumps and SBO SBZ TB. A jump moves PC by displacement words from the next instruction: target = address + 2 + 2 × displacement. A CRU bit instruction adds the signed displacement to R12 / 2.
III	opcode (6 bits) D Ts S	1 to 2	COC CZC XOR: D is a register
IV	opcode (6 bits) C Ts S	1 to 2	LDCR STCR: C is the bit count, 1 to 15, and 0 means 16
V	opcode (8 bits) C W	1	SLA SRA SRC SRL: C is the count (0: take it from the low four bits of R0, and 0 there means 16), W the register
VI	opcode (10 bits) T S	1 to 2	ABS B BL BLWP CLR DEC DECT INC INCT INV NEG SETO SWPB X
VII	opcode (11 bits), 5 unused bits	1	CKOF CKON IDLE LREX RSET RTWP
VIII	opcode (11 bits), 1 unused bit, register (4 bits); an immediate word follows for all but STWP and STST	1 to 2	AI ANDI CI LI LIMI LWPI ORI STST STWP (LIMI and LWPI have no register: the register field is unused)
IX	opcode (6 bits) D Ts S	1 to 2	DIV MPY XOP: D is a register, or the XOP number 0 to 15

The sixteen-bit CRU transfer count C: LDCR and STCR use a byte operand when C is 1 to 8 (so the source is the high byte of a register or the byte at an address) and a word operand when C is 9 to 15 or 0 (16).

Not described

Known, not yet covered

Reference: the order of the memory accesses within one instruction (source read, destination read, destination write) and the bus cycles of the TI-99/4A’s multiplexer.

Unknown

Reference: the fill bits of STCR for a count below 8 or 16 and whether a byte STCR with an odd address behaves as described by every source: the sources read were summaries.

TMS9900 Instruction Set – Addressing modes and formats