PowerPC Instruction Set

Introduction

PowerPC is the RISC instruction set that IBM, Motorola and Apple defined in 1991 from IBM's POWER architecture. It ran the Power Macintosh (G3, G4 and G5), the Nintendo GameCube and Wii, the Xbox 360, the PlayStation 3 (the Cell's PPE) and many embedded controllers; today's descendant, the Power ISA, runs IBM's POWER servers, where 64-bit little-endian code (ppc64le) is common on Linux. Every instruction is 32 bits long and there are 32 general registers. The explorer's own disassembler reads 32-bit and 64-bit PowerPC, the Power ISA up to 3.0 (and most of 2.07), AltiVec, VSX and the Gekko paired singles, as processor models you choose.

The instructions are on the pages in the side menu; each has an anchor, so a disassembled instruction in the explorer links to its entry. A PowerPC program opens in the explorer today as an ELF file: the byte order comes from the file, and the options bar picks the processor model, the register names, the simplified mnemonics, the condition register notation and how branch targets are written.

The processor models

Status of an instruction

Registers

• General registers r0 to r31, 32 bits (64 on 64-bit models). In an address, an ra of 0 means the value zero, not r0.
• Floating-point registers f0 to f31, 64 bits, and the status register FPSCR.
• Condition register CR: eight 4-bit fields cr0 to cr7, each with the bits LT, GT, EQ and SO; condition bit numbers run 0 to 31. Integer instructions with a dot set cr0, floating-point ones cr1, vector compares with a dot cr6.
• Link register LR and count register CTR, and the fixed-point exception register XER (SO, OV, CA).
• Vector registers v0 to v31 with VSCR and VRSAVE (AltiVec), and the VSX registers vs0 to vs63 (the floating-point registers are the high halves of vs0 to vs31, the vector registers are vs32 to vs63).
• Special-purpose registers read and written with mfspr and mtspr; the numbers the explorer names are listed on the supervisor page. The Gekko adds GQR0 to GQR7, HID2, WPAR, DMA_U and DMA_L.

Bits and fields are numbered from the most significant end: bit 0 is the top bit of a word, bit 31 the bottom bit. Every table on these pages follows that.

Instruction formats

The primary opcode is bits 0 to 5. The extended opcode, where there is one, sits in the field named below.

Simplified mnemonics

With simplified mnemonics on (the default) an instruction that has a shorter assembler name is written with it; with them off it is shown as encoded.

Options

How the decoder was checked

The decoder is the explorer's own; llvm only checks it. About 1.2 million 32-bit words (every primary opcode with every 10-bit extended opcode and several fills, register-field edges, immediate extremes, every BO and BI, every SPR number and a seeded random sample), in both byte orders, were compared with llvm-mc --disassemble. Where llvm writes a simplified mnemonic, its text was assembled back with llvm-mc and had to give the same word. llvm's disassembler ignores the processor model, so it cannot check which model has which instruction: that comes from the manuals, with the paired singles checked against the opcode tables of the Dolphin emulator. Compiler output (clang and lld, 32-bit, 64-bit and little-endian 64-bit) was compared with llvm-objdump.

Not described

Known, not yet covered

• Reference and viewer: the ISA 3.1 (POWER10) instructions, including the 8-byte prefixed forms, and the ISA 3.0 and 3.1 vector and BCD instructions beyond those listed on the AltiVec page.
• Reference and viewer: decimal floating point, quad-precision floating point, transactional memory.
• Reference and viewer: Book E, the e500 SPE and VLE (16-bit) encodings, and the other embedded and hypervisor cache-inhibited instructions.
• Reference and viewer: VMX128 of the Xbox 360 Xenon.
• Viewer: the GameCube and Wii DOL and REL files, Wii WAD, PS3 SELF and PRX, Xbox 360 XEX, Mac OS PEF, which will use this decoder.

Unknown

• Reference: which instructions each shipped chip decodes beyond the architecture books (for example optional instructions of the 603 and 604); the models follow the manuals.
• Reference: the special-purpose register names beyond the ones listed on the supervisor page.

Links