PowerPC Branches and Condition Register

Introduction

PowerPC has no delay slots. A branch takes effect immediately, and the instruction after it is simply the next one. The target of b and bc is the address of the branch plus a signed displacement (a multiple of four), or, with the a (absolute) form, the displacement itself. bclr branches to the address in the link register (LR) and bcctr to the count register (CTR); bctar uses the target address register. Every branch has an l (link) form that writes the address of the next instruction into LR, which is how a call is made. A function returns with blr, a bclr that always branches.

The condition register, CR, is eight 4-bit fields, cr0 to cr7. Each field holds the bits LT, GT, EQ and SO (summary overflow, a copy of XER[SO] after an integer record form or compare). A conditional branch names one of the 32 bits of the condition register in its BI field, and says what to test in its BO field. Most assembly programs never write BO and BI: they use the simplified mnemonics. The condition register logic instructions combine bits of it, and the move instructions copy fields to and from general registers.

The BO and BI fields

BI (5 bits) selects the condition register bit: BI = 4 × field + bit, where the bit within a field is 0 for LT, 1 for GT, 2 for EQ and 3 for SO. So BI = 2 is cr0[EQ] and BI = 6 is cr1[EQ]. BO (5 bits) says whether to test the bit, whether to decrement the count register and test it, and gives a prediction hint. In the manuals' numbering (bit 0 of BO is its most significant bit) the values are:

The low bit y (with the z bit above it, the pair the later manuals call at) is a prediction hint. The z bits are ignored by the hardware but should be zero. The explorer writes the hint as a trailing + (predict taken) or - (predict not taken), as in bne- cr1, target. For bcctr and bctar the count register cannot be decremented, so a BO that decrements CTR is an invalid form.

Simplified branch mnemonics

With simplified mnemonics on (the default), the explorer writes a conditional branch by its condition. The condition names are lt, gt, eq, so for a set bit and ge (not LT), le (not GT), ne (not EQ), ns (not SO) for a clear bit; b + condition is a branch to a target, + lr a branch to the link register and + ctr one to the count register; an l after that links. The condition register field is the first operand, and is left out when it is cr0.

A BO that has no simplified name (a branch always with a nonzero BI, for example) is shown in full as bc, bclr or bcctr.

Branches and system calls

Condition register logic and moves

The logic instructions take condition register bit numbers (0 to 31, the same numbering as BI) for bt, ba and bb. The fields are named bf and bfa (field numbers 0 to 7), which the explorer writes as cr0 to cr7 or as plain numbers (an option).

The branch-and-link forms return through LR, and mflr and mtlr (mfspr and mtspr with the link register) save and restore it. The compare instructions and the record forms (add., andi.) set condition register fields; see the integer page.

Not described

Known, not yet covered

• Reference: the Book E and embedded branch variants and the ISA 3.1 prefixed (8-byte) instructions.
• Reference and viewer: the exact meaning of the BH field hints (return, call, not a subroutine) is stated only as “a hint”.
• Viewer: following a jump through a register (bctr after a table load) to its target.

Unknown

• Reference: none known.

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