PowerPC Floating Point

Introduction

PowerPC has 32 floating-point registers, f0 to f31, each 64 bits wide and holding an IEEE 754 double-precision value, and the 32-bit floating-point status and control register FPSCR. The single-precision instructions (those ending in s, with primary opcode 59) round their result to single precision; the double-precision ones (primary opcode 63) do not. A single-precision load converts the value to double, and a single-precision store converts it back. There is no separate set of single registers.

A record form (a dotted mnemonic such as fadd.) copies the four exception summary bits of the FPSCR into cr1. The multiply-add instructions are fused: the product is not rounded before the addition. In the table, frt and frs are the same bits of the word (destination and source), and fra, frb and frc are the source registers. Most of the entries here are available in every PowerPC model; fsqrt and fsqrts are optional in the architecture and the 750 and the G4 lack them.

The same registers are the first halves of the vector-scalar registers (see AltiVec and VSX), and the Gekko and Broadway processors treat them as pairs of singles (see paired singles).

Floating-point loads and stores

The operand forms are as for the integer loads and stores: d(ra) is a displacement from a base register (a zero ra means the value 0, not r0), the x forms add two registers, and the u forms write the address back to ra.

Single-precision arithmetic

Double-precision arithmetic

Compare, convert, round and move

The conversions to integer leave the result in the low bits of a floating-point register (store it with stfiwx or stfd, or move it with a VSX instruction); the z forms round toward zero, the others use the rounding mode of the FPSCR. The compare instructions write the field bf of the condition register.

The FPSCR

The FPSCR holds the exception status bits, the exception enables and the rounding mode. The rounding mode is its two low bits: 0 round to nearest, 1 toward zero, 2 toward plus infinity, 3 toward minus infinity. The instructions move it to and from floating-point and condition registers. Each has a record form that copies the exception summary into cr1. The ISA 3.0 forms of mffs (the last six rows) also change the rounding modes or clear the enables in the same step; they are decoded here although the explorer's table keeps them with the supervisor instructions.

Not described

Known, not yet covered

• Reference and viewer: decimal floating point (dadd, dmul and the rest, POWER6 and later), and the ISA 3.0 quad-precision instructions (xsaddqp and others).
• Reference: the layout of the FPSCR bits beyond the rounding mode, and the exact exception behaviour of each instruction.
• Reference: the VMX128 floating-point extension of the Xbox 360.

Unknown

• Reference: none known.

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