PowerPC Supervisor Instructions

Introduction

These are the instructions of the operating-system (supervisor) level: the ones a user program cannot run. In user mode they raise a privileged-instruction exception. They return from interrupts, read and write the machine state register, manage the segment registers of the 32-bit architecture and the segment lookaside buffer (SLB) of the 64-bit one, and invalidate translation lookaside buffer (TLB) entries. The explorer marks them “supervisor” in its notes. The move to and from special-purpose registers (mfspr, mtspr) is on the integer page; the supervisor registers they name are listed below. dcbi (invalidate a data cache block) is here too; the other cache instructions are on the loads and stores page.

The machine state register

The MSR holds the processor's mode. It is read with mfmsr and written with mtmsr (and mtmsrd on 64-bit implementations); rfi and the other return instructions restore it from SRR1. The manuals number the bits from the most significant end. The 32-bit architecture's register is 32 bits wide; in a 64-bit implementation the register is 64 bits wide and the same bits are 32 higher.

Other bits (power management, the little-endian interrupt mode, the AltiVec and VSX availability bits, the performance monitor bit and the transactional memory bits) differ between models and are not described here.

The instructions

The ISA 3.0 forms of mffs that change the floating-point rounding modes (mffsce, mffscrn and the others) are on the floating point page.

Supervisor special-purpose registers

mfspr and mtspr take a 10-bit register number; the two halves of the number are swapped in the instruction word, which the explorer undoes. With simplified mnemonics on, the explorer writes the register by name (mfsrr0, mtsprg1). The registers it names are these; any other number is written as a number.

The user-readable registers (XER, LR, CTR, VRSAVE, the time base and the user performance monitor registers) are on the overview.

Not described

Known, not yet covered

• Reference and viewer: the Book E and embedded supervisor instructions (wrtee, tlbwe, tlbre, the device control registers), and the hypervisor and ultravisor instructions of ISA 3.0 and later beyond those listed.
• Reference: the meaning of every field of tlbie in its ISA 3.0 radix and hash forms, and of the L field of mtmsr.
• Reference: the MSR bits not in the table, and the layouts of the BAT, SDR1 and HID registers.

Unknown

• Reference: which models implement the optional tlbia; the pages follow the architecture manuals.

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