PowerPC Integer Arithmetic, Logic and Shifts

Introduction

PowerPC is a load-store architecture: arithmetic works on registers (the 32 general registers r0 to r31), and only the load and store instructions touch memory. Most instructions name a destination and two sources, three registers in all. In a 32-bit implementation the registers are 32 bits wide; in a 64-bit one they are 64 bits wide and the word instructions (add, slw, cmpw) work on the low 32 bits, while the doubleword instructions (mulld, sld, rldicl) are available only on 64-bit models (the “Available in” column says 64-bit).

Many entries have suffixed forms, written in the Mnemonic column. A trailing dot (add.) is the record form: it also sets cr0 to the sign of the result (LT, GT, EQ) and a copy of XER[SO]. An o (addo) enables overflow detection: the instruction sets XER[OV] and the sticky XER[SO]; addo. does both. Instructions that carry set or use XER[CA]. Several instructions are best read by their simplified mnemonics.

In the table, rt and rs are the same bits of the word (the destination when written, the source when read), ra and rb are the other registers, si is a signed 16-bit immediate and ui an unsigned one. ra0 in a manual is ra where the value 0 replaces register r0; the table writes ra and notes it.

Arithmetic

Compare

A compare writes one condition register field, bf (cr0 if left out), with LT, GT, EQ and a copy of XER[SO]. The l operand chooses a 32-bit (0) or 64-bit (1) comparison; the simplified mnemonics cmpw, cmpd, cmplw, cmpld, cmpwi and cmpdi write it.

Trap

A trap instruction raises a trap exception when a comparison of its operands is true under the condition bits of to (5 bits: less than, greater than, equal, unsigned less than, unsigned greater than). The simplified mnemonics (twlt, tweqi, tdgti ...) name the condition, and trap is tw 31, 0, 0, the unconditional trap used for breakpoints.

Logical, sign extension and bit counting

The logical instructions write ra and read rs (the manuals' names), the reverse of the arithmetic ones.

Rotate and shift

The rotate instructions rotate rs left, then combine it with a mask of ones from bit mb to bit me (in the manuals' numbering, bit 0 on the left of the 32-bit word); the shifts are special cases of them, and the simplified mnemonics name the useful ones (slwi, srwi, clrlwi, rotlwi, extrdi ...). The doubleword rotates take a 6-bit shift and mask (sh, mb or me), written in the instruction word with its high bit in a separate position.

Special registers and the time base

mfspr and mtspr move between a general register and a special-purpose register (SPR). The user-level ones are XER (1), LR (8), CTR (9), VRSAVE (256) and the time base (268, 269); the supervisor registers are on the supervisor page. With simplified mnemonics on, the explorer writes mflr r0 for mfspr r0, 8, mtctr r9, mtxer, mfsrr0 and so on.

Simplified mnemonics

With simplified mnemonics on (the default) the explorer writes these instead of the encoded form; with them off it shows the instruction as encoded. The branch ones are on the branches page.

Not described

Known, not yet covered

• Reference and viewer: the Book E and embedded integer instructions (multiply-accumulate, mulhhw and the like), and the ISA 3.1 prefixed (8-byte) instructions with their new integer forms.
• Reference: the exact condition register and XER results of each instruction beyond the record and overflow forms noted above.

Unknown

• Reference: none known.

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