PowerPC AltiVec and VSX

Introduction

AltiVec (Apple called it Velocity Engine, IBM and the Power ISA call it VMX) adds 32 vector registers of 128 bits and instructions that work on 16 bytes, 8 halfwords or 4 words at a time. It appeared in the PowerPC 7400 (G4) and the 970 (G5), and is in the Cell PPE and in POWER6 and later. VSX, the vector-scalar facility of Power ISA 2.06 (POWER7), adds 64 registers that hold either a vector or a floating-point scalar, double-precision and single-precision vector arithmetic, and a second family of loads, stores and logical operations. Power ISA 2.07 (POWER8) and 3.0 (POWER9) added 64-bit integer elements, quadword arithmetic, AES, SHA and polynomial multiplication to the vector facility, and many VSX instructions. This page lists every AltiVec and VSX instruction the explorer decodes, including the vector and VSX loads and stores, which the explorer's links send here. The Gekko paired singles use some of the same opcodes and are on the Gekko page; a variant has one or the other.

The “Available in” column names the first level that has the instruction: AltiVec (G4, G5, Cell, POWER6 and later), VSX (POWER7 and later), ISA 2.07 (POWER8 and later), ISA 3.0 (POWER9 and later), ISA 3.1 (POWER10) and Cell only. An instruction marked ISA 2.07 or later also needs the vector or VSX facility.

Registers

• v0 to v31: the 32 vector registers, 128 bits each. They are the registers vrt, vra, vrb and vrc of the tables below, five bits each.
• VSCR: the vector status and control register, read with mfvscr and written with mtvscr; see below.
• VRSAVE: special-purpose register 256, a 32-bit mask the operating system and compilers use to record which vector registers a program is using. It has no effect on the hardware.
• vs0 to vs63 (VSX): 64 registers of 128 bits. A VSX instruction names a register with six bits: five in the usual field and the sixth in a separate bit of the word (xt, xa, xb and xc below). vs0 to vs31 overlay the floating-point registers f0 to f31, which are the high doubleword of each; vs32 to vs63 are the vector registers v0 to v31.

The vector registers hold elements in the order of the machine's byte order: element 0 is the one at the lowest address in big-endian mode, which the manuals and the tables use for the left-most element.

The VSCR

The vector status and control register has two bits that matter to a program: NJ (non-Java mode, which turns on faster, less exact handling of denormal floating-point values) and SAT (saturation: a sticky bit that any saturating instruction sets when a result was clamped). mfvscr and mtvscr move the register through a vector register. SAT stays set until a program clears it with mtvscr.

Saturation

Most integer instructions come in two forms. The modulo form (vaddubm, vadduwm) wraps around like ordinary integer arithmetic. The saturate form (vaddubs, vaddsws, the pack and convert instructions that end in s) clamps a result that does not fit to the largest or smallest value of the element, and sets VSCR[SAT]. A mnemonic names the element after the operation: b byte, h halfword, w word, d doubleword, q quadword; u unsigned and s signed.

The instruction forms

The AltiVec instructions use primary opcode 4 and three forms (see instruction formats; bit 0 is the most significant bit):

The VSX instructions use primary opcode 60 (and 61, 57, 56 and 62 for some loads and stores) with the XX forms: XX2 (one source xb), XX3 (two sources xa, xb), XX4 (three sources, with xc) and for the compares an XX3 form whose record bit is bit 21. The extra register bits are bit 29 (AX), 30 (BX), 31 (TX) and, in XX4, 28 (CX); in the DQ form the TX bit is bit 28. The loads and stores of primary opcode 31 are in the X form.

Add and subtract

Maximum, minimum and average

Shift and rotate

Logical

Multiply and sum across

The odd and even multiplies take every second element and produce elements twice as wide. The sum-across instructions add groups of elements into words. The multiply-sum and multiply-add instructions are in the four-register section below.

Merge and pack

Unpack, estimate, round, count and gather

These take one source register (vrb); the vra field of the encoding is not used.

Floating-point

AltiVec floating-point works on four single-precision values. There is no vector floating-point multiply: use vmaddfp with a zero addend. Floating-point comparisons are in the compare section and conversions in the conversion section.

Conversion between integer and floating-point

The last operand is a 5-bit scale: the integer is divided or multiplied by 2 to the power of that number.

Splat and the status register

A splat copies one element, or an immediate, to every element of the result. The element number is 4, 3 or 2 bits wide (16 bytes, 8 halfwords, 4 words); the remaining bits of the field must be zero.

Four-register instructions: permute, select, multiply-add

The VA form names a fourth register. vperm is the general byte shuffle: each byte of vrc picks one of the 32 bytes of vra and vrb (the low five bits of the byte). vsel takes each bit from vrb where the bit of vrc is 1 and from vra where it is 0.

Compare

A vector compare writes all ones into each element where the relation holds and all zeros elsewhere. The dotted form (the VC form with Rc set) also sets condition register field 6, so a program can branch on “all elements” or “no element” without moving the result. vcmpbfp tests whether each value is within the bounds given by the other register; its result bits are not all ones or all zeros.

AES, SHA, polynomial multiply and bit permute

Power ISA 2.07 added instructions for the AES rounds (the cipher and inverse cipher steps and the S-box), the SHA-256 and SHA-512 sigma functions, carry-less (polynomial) multiplication for CRC and GCM, and a bit permute.

AltiVec loads and stores

All use the X form with an indexed address (ra|0) + rb. lvx and stvx ignore the low four bits of the address, so they are always 16-byte aligned; to read an unaligned vector, a program uses lvsl or lvsr to build a permute control vector and combines two aligned loads with vperm. The element loads and stores move one byte, halfword or word to or from the position the address selects. The l suffix (“last”) hints that the data will not be used again soon. The four dst forms start a prefetch stream; dss stops one.

VSX scalar arithmetic

The scalar instructions work on the first doubleword of a VSX register (single-precision ones on a value in the double-precision register format). The multiply-add forms come in two types: type A overwrites the addend register, type M overwrites the multiplicand. Operands are xt, xa, xb.

VSX vector arithmetic

The vector instructions work on two double-precision (dp) or four single-precision (sp) values. Operands are xt, xa, xb.

VSX logical, merge and permute

VSX compare and test

The vector compares write a mask like the AltiVec ones; the dotted form (record bit 21) also sets condition register field 6. xscmpudp, xscmpodp, xscmpexpdp and the test instructions write a condition register field bf instead of a register.

VSX convert, round, estimate, square root and sign

All of these take one source register: xt, xb.

VSX permute, shift, splat and select

VSX loads and stores

These are indexed, (ra|0) + rb, in the X form. lxvl and stxvl move a number of bytes given in the high byte of rb.

Moves between general registers and VSX registers

Quadword load and store

These move 16 bytes to or from an even-odd pair of general registers. They are 64-bit instructions of Power ISA 2.01 and later; they are not vector instructions but are listed here with the other 16-byte accesses.

Not described

Known, not yet covered

• Reference and viewer: VMX128, the Xbox 360 Xenon extension with 128 vector registers and its own encodings.
• Reference and viewer: the quad-precision floating-point instructions of Power ISA 3.0 (xsaddqp and the others), the vector instructions that Power ISA 3.1 added, and the 8-byte prefixed instructions of Power ISA 3.1.
• Reference and viewer: decimal floating point, and the transactional memory instructions.
• Reference and viewer: the remaining Power ISA 3.0 vector instructions (vextu*, vinsert*, vslv, vsrv, vrlwnm and others) that the explorer does not decode.

Unknown

• Reference: none known.

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