PowerPC Loads, Stores and Cache Control

Introduction

Only loads and stores touch memory. The effective address is either a displacement form, d(ra), a signed 16-bit displacement added to a base register, or an indexed form (the mnemonic ends in x), ra, rb, the sum of two registers. In both, a zero ra field means the value 0 and not the register r0; in the table that is the operand written ra in a memory operand. The update forms (a u in the name) also write the effective address back to ra, and need ra to be non-zero. A load that ends in z zero-extends, one that ends in a (algebraic) sign-extends.

Memory is big-endian unless the processor runs in little-endian mode (see the byte order option). The byte-reversed loads and stores (lwbrx and the others) exchange the byte order of the access and are how a program reads data of the other byte order. The doubleword forms need a 64-bit model.

The floating-point loads and stores are on the floating point page (for example lfs and stfd), the vector loads and stores on the AltiVec page (lvx, stvx, the data stream instructions), the vector-scalar ones on its VSX section (lxvd2x and the others, and the quadword lq), and the quantized loads of the Gekko on its page.

Integer loads

Integer stores

Atomic instructions

An atomic read-modify-write is a load-and-reserve (lwarx) followed by a store-conditional (stwcx.) to the same address, with the update in between. The store succeeds, and sets cr0[EQ], only if no other processor has written the reserved location since the load; otherwise the program branches back and tries again. The store-conditional instructions always set cr0, so they only exist as dotted mnemonics. The optional eh operand of a load-and-reserve is a hint that the reservation will be held in a lock loop. The ISA 3.0 lwat, ldat and their stores perform one fetch-and-operate (add, increment, swap and others, chosen by fc) in a single instruction.

Cache control and synchronisation

The cache instructions act on the cache block that holds the effective address. The data cache block touch instructions (dcbt, dcbtst) are prefetch hints and never fault. sync orders all earlier storage accesses before any later one; with simplified mnemonics on the explorer writes its L field as lwsync (1, a lighter barrier) and ptesync (2). eieio orders accesses to I/O and to other storage separately. The supervisor-only dcbi is on the supervisor page, and the Gekko's dcbz_l on its own page.

Not described

Known, not yet covered

• Reference: alignment rules and the exceptions an unaligned access raises on each model; the memory-ordering rules in detail.
• Reference: the meaning of the th operand of dcbt and of the fc function codes of the atomic instructions beyond “chosen by FC”.
• Reference and viewer: the Book E and embedded cache instructions, and the ISA 3.1 prefixed (8-byte) loads and stores.

Unknown

• Reference: none known.

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