PowerPC Gekko and Broadway Paired Singles

Introduction

The Nintendo GameCube's Gekko and the Wii's Broadway are PowerPC 750 cores with an added set of paired-single instructions and a locked cache. A paired single treats a 64-bit floating-point register as two 32-bit single-precision values, slot 0 (ps0, the same value an ordinary floating-point instruction sees) and slot 1 (ps1). One instruction then does two single-precision operations, which is how these consoles do their vertex and matrix arithmetic. The quantized loads and stores (psq_l, psq_st) convert between pairs of integers or singles in memory and the registers, under the control of the eight graphics quantization registers. Broadway runs the same instruction set as Gekko at a higher clock.

These instructions use primary opcode 4, which is also the AltiVec opcode, and opcodes 56, 57, 60 and 61, which the later Power ISA gives to other instructions. A processor has one set or the other, so the explorer decodes the paired singles only for the Gekko and Broadway models. Every record form (a dotted mnemonic, such as ps_add.) copies the floating-point exception summary bits to CR1, as the other floating-point instructions do. The paired singles need the paired single enable and the quantized load and store enable bits of HID2 to be set; the bit positions are not described here.

The graphics quantization registers

The eight registers GQR0 to GQR7 are the special-purpose registers 912 to 919, supervisor registers read and written with mfspr and mtspr. The I field of a quantized load or store picks one. Each register has four fields (bits numbered from the most significant end, as in the manual):

The types: 0 is a single-precision float (the scale is ignored), 4 is an unsigned 8-bit integer, 5 an unsigned 16-bit integer, 6 a signed 8-bit integer and 7 a signed 16-bit integer. The other values are reserved. The W bit of the instruction chooses between a pair (W = 0) and a single value (W = 1; a load then sets ps1 to 1.0). The registers HID2 (920), WPAR (921), DMA_U (922) and DMA_L (923) belong to the same extension: the write-gather pipe address and the direct memory access to and from the locked cache.

The instructions

Slots are written ps0 and ps1. The “form” of the quantized loads and stores is the D form with a 12-bit displacement, with the W bit and the 3-bit I field in the place of the low bits of a 16-bit displacement.

Quantized loads and stores

Arithmetic

Compare, move and merge

Locked cache

How it was checked

llvm has no support for the paired singles, so these instructions have no llvm check. The encodings and the operations were checked against the PowerPC 750CL user's manual and the Gekko user's manual, and against the instruction tables of the Dolphin emulator's interpreter (Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp), which lists each paired-single opcode with its extended opcode number.

Not described

Known, not yet covered

• Reference: the bit positions of the HID2 enable bits, the layout of WPAR, DMA_U and DMA_L, and the locked cache configuration.
• Reference: the exact rounding and exception behaviour of each paired-single operation (the table gives the operation only).
• Viewer: showing the quantization type of a psq_l from the value of the register.

Unknown

• Reference: the paired singles have no second implementation to compare with other than Dolphin's tables; there is no llvm decoding for them.

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