Introduction
The CP1610 is a 16-bit processor made by General Instrument, best known as the processor of the Mattel Intellivision (1979). It has eight 16-bit registers, one of which is the program counter, a simple set of arithmetic and logic instructions (no OR), branches with an external condition input, and a prefix, SDBD, that makes the next instruction work on two 8-bit values instead of one 16-bit one. Its instructions are not bytes or words but decles: ten-bit words, because the console’s program ROMs are ten bits wide. An address counts decles, not bytes, and a program is 1 to 3 decles per instruction.
In a ROM file each decle is stored as a 16-bit big-endian word whose top six bits are unused (zero). The explorer’s disassembler reads such files: two bytes make a decle, and the address of a decle is its number, counted from the load address (for example $5000). Because a listing is drawn byte by byte, every byte at an odd offset shows as the second half of a decle.
The pages: registers and the status word, addressing modes, the formats and SDBD, every instruction and the opcode map. The 1,024 possible decles are all instructions or parts of one, except the jumps with a reserved interrupt field.
Statuses in the disassembly
| Status | Meaning |
|---|---|
| Documented | An instruction in the processor’s documentation as jzIntv’s author and the Intellivision community describe it. |
| Undocumented | An instruction with the top six bits of its 16-bit word set (ignored by the processor), or one used after SDBD in a way the documentation does not allow (a direct address, a store, MVOI or the stack): jzIntv’s own tools disagree about these. |
| Illegal | A jump whose interrupt field is 3 (reserved), or an instruction cut short. Shown as DECLE words. |
| Odd address | A byte at an odd offset in the file: the second half of a decle. |
Notation
The disassembly follows jzIntv’s assembler (as1600): upper-case mnemonics, hexadecimal with a $, operands source first except for the stores:
MVI@ R4, R0, MVO R0, $0200, MVII #$0002, R0, ADDR R1, R2, BEQ $5010, BEXT $5010, $2, JSR R5, $5100.
The aliases the assembler uses are shown as the instruction: TSTR (MOVR of a register to itself), JR (MOVR to R7), CLRR (XORR with itself),
PSHR and PULR (MVO@ to and MVI@ from R6). A branch shows the address it goes to. The plain syntax option writes lower case.
Not described
Known, not yet covered
- Reference: the interrupt acceptance sequence, the Intellivision’s memory map, the STIC, PSG and EXEC ROM entry points, Intellicart and LTO Flash extended instructions, and the 16-bit-wide memory forms of the cartridge formats (.bin, .int, .rom with a .cfg file, .itv): later format pages.
- Reference: cycle counts with SDBD.
- Viewer: the disassembler decodes every decle as code: it does not separate code from data and does not follow jumps. An instruction after an SDBD is decoded in its SDBD form even when the SDBD is the second decle of something else.
Unknown
- Reference: what the low bit of NOP and SIN does, what SIN does exactly, and the effect of SDBD before an instruction that cannot use it.
- Reference: the cycle counts of the register-register arithmetic instructions: jzIntv’s summary says 7 when the destination is R6 or R7 for all of them; the Intellivision wiki lists only MOVR that way.
- Reference: the register, flag and memory effects were not run on an emulator core (see the checks in the project notes): they come from the jzIntv documentation.