Introduction
Each row gives the instruction, the decle values (hexadecimal; a range is every register or mode variant), what it does, the flags it changes (S sign,
Z zero, O overflow, C carry; see the status word) and the cycles. Cycles are
the General Instrument microcycle counts as jzIntv’s summary gives them. Where the two sources differ it is said.
Control
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
HLT | 0000 | Halt the processor. | none | 4 |
SDBD | 0001 | Set double byte data: the next instruction works on two 8-bit values (see SDBD). Not interruptible. | none | 4 |
EIS | 0002 | Enable the interrupt system. Not interruptible. | none | 4 |
DIS | 0003 | Disable the interrupt system. Not interruptible. | none | 4 |
TCI | 0005 | Terminate the current interrupt. Not interruptible. | none | 4 |
CLRC | 0006 | Clear carry. Not interruptible. | C | 4 |
SETC | 0007 | Set carry. Not interruptible. | C | 4 |
Jumps
Three decles: 0004, then bb pppppp ii (bb the return register, p the upper six address bits, ii the interrupt mode), then the lower ten address bits.
The jumps with a return register save the address after the instruction in R4, R5 or R6; E enables and D disables the interrupt system. A pair (bb = 3, ii = 3) or any bb with ii = 3 is reserved.
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
J | 0004 bb = 3, ii = 0 | Jump. | none | 12 |
JE | 0004 bb = 3, ii = 1 | Jump and enable interrupts. | none | 12 |
JD | 0004 bb = 3, ii = 2 | Jump and disable interrupts. | none | 12 |
JSR | 0004 bb = 0 to 2, ii = 0 | Jump to subroutine: the return address goes in R4, R5 or R6 (bb). JSR R5, addr is the assembler’s CALL. | none | 12 |
JSRE | 0004 bb = 0 to 2, ii = 1 | Jump to subroutine and enable interrupts. | none | 12 |
JSRD | 0004 bb = 0 to 2, ii = 2 | Jump to subroutine and disable interrupts. | none | 12 |
One register
The last three bits of the decle are the register (GSWD only the last two: R0 to R3). The cycles are 6, 7 when the destination is R6 or R7 (jzIntv’s summary; the wiki says 6).
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
INCR | 0008-000F | Add one to the register. | S Z | 6 |
DECR | 0010-0017 | Subtract one from the register. | S Z | 6 |
COMR | 0018-001F | Complement the register (one’s complement). | S Z | 6 |
NEGR | 0020-0027 | Negate the register (two’s complement). | S Z O C | 6 |
ADCR | 0028-002F | Add the carry to the register. | S Z O C | 6 |
GSWD | 0030-0033 | Get the status word into bits 15 to 12 and 7 to 4 of the register (R0 to R3). | none | 6 |
NOP | 0034-0035 | No operation (0035 is shown as NOP2 by jzIntv’s listing). | none | 6 |
SIN | 0036-0037 | Software interrupt: pulses the PCIT pin (0037 is SIN2). | none | 6 |
RSWD | 0038-003F | Restore the status word from bits 7 to 4 of the register. | S Z O C | 6 |
Shifts and rotates
R0 to R3 only; bit 2 of the decle makes the shift by two positions (the cycle count then grows by two). Not interruptible. The rotates and shifts through the carry use O for the second bit of a two-position shift.
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
SWAP | 0040-0047 | Swap the two bytes (by 2: copy the low byte into both bytes). | S Z | 6 |
SLL | 0048-004F | Shift logical left. | S Z | 6 |
RLC | 0050-0057 | Rotate left through carry. | S Z O C | 6 |
SLLC | 0058-005F | Shift logical left through carry. | S Z O C | 6 |
SLR | 0060-0067 | Shift logical right. | S Z | 6 |
SAR | 0068-006F | Shift arithmetic right. | S Z | 6 |
RRC | 0070-0077 | Rotate right through carry. | S Z O C | 6 |
SARC | 0078-007F | Shift arithmetic right through carry. | S Z O C | 6 |
Register to register
Source register in bits 5 to 3, destination in bits 2 to 0; the result goes to the destination. 6 cycles, 7 when the destination is R6 or R7. The aliases are below.
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
MOVR | 0080-00BF | Move the source register to the destination. | S Z | 6 |
ADDR | 00C0-00FF | Add the source to the destination. | S Z O C | 6 |
SUBR | 0100-013F | Subtract the source from the destination. | S Z O C | 6 |
CMPR | 0140-017F | Compare: destination minus source; the result is not stored. | S Z O C | 6 |
ANDR | 0180-01BF | AND the source into the destination. | S Z | 6 |
XORR | 01C0-01FF | Exclusive OR the source into the destination. | S Z | 6 |
TSTR | 0080, 0089, 0092, 009B, 00A4, 00AD, 00B6, 00BF | Alias: MOVR of a register to itself, to test it. | S Z | 6 |
JR | 0087, 008F, 0097, 009F, 00A7, 00AF, 00B7 | Alias: MOVR to R7: jump to the address in the register. | S Z | 6 |
CLRR | 01C0, 01C9, 01D2, 01DB, 01E4, 01ED, 01F6, 01FF | Alias: XORR of a register with itself: clear it. | S Z | 6 |
Branches
Two decles, the second the displacement (see branch targets). Bit 5 of the first selects backward. The condition is in bits 2 to 0, and bit 3 takes the opposite condition. 7 cycles, 9 when the branch is taken; B always takes 9 and NOPP 7. The two decles are listed forward then backward.
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
B | 0200, 0220 | Branch always. | none | 9 |
BC | 0201, 0221 | Branch on carry (C = 1). | none | 7 |
BOV | 0202, 0222 | Branch on overflow (O = 1). | none | 7 |
BPL | 0203, 0223 | Branch on plus (S = 0). | none | 7 |
BEQ | 0204, 0224 | Branch if equal or zero (Z = 1). | none | 7 |
BLT | 0205, 0225 | Branch if less than (S xor O = 1). | none | 7 |
BLE | 0206, 0226 | Branch if less than or equal (Z or (S xor O) = 1). | none | 7 |
BUSC | 0207, 0227 | Branch if the sign is not the carry (S xor C = 1). | none | 7 |
NOPP | 0208, 0228 | Branch never: a two-decle no-operation. jzIntv’s listing calls a NOPP used to skip over the next decle a SKIP. | none | 7 |
BNC | 0209, 0229 | Branch on no carry (C = 0). | none | 7 |
BNOV | 020A, 022A | Branch on no overflow (O = 0). | none | 7 |
BMI | 020B, 022B | Branch on minus (S = 1). | none | 7 |
BNEQ | 020C, 022C | Branch if not equal or not zero (Z = 0). | none | 7 |
BGE | 020D, 022D | Branch if greater than or equal (S xor O = 0). | none | 7 |
BGT | 020E, 022E | Branch if greater than (Z or (S xor O) = 0). | none | 7 |
BESC | 020F, 022F | Branch if the sign equals the carry (S xor C = 0). | none | 7 |
BEXT | 0210-021F, 0230-023F | Branch if external condition n (the low four bits) is true. The Intellivision connects none; jzIntv takes the branch always. | none | 7 |
Memory instructions
The mode m (bits 5 to 3) and the register r (bits 2 to 0). Cycles by mode: direct, immediate, indirect (R1 to R5) and stack (R6). With SDBD the counts are not given. These instructions are not interruptible when they store (MVO). Forms: direct (m = 0), indirect (m = 1 to 5), stack (m = 6), immediate (m = 7).
| Instruction | Opcode | What it does | Flags | Cycles |
|---|---|---|---|---|
MVO | 0240-0247 direct0248-026F indirect0270-0277 stack (PSHR)0278-027F immediate (MVOI) | Move out: the register is stored in memory. MVO R0, $0200, MVO@ R0, R4. MVOI writes the register over its own immediate operand: not useful. | none | dir 11, imm 9, ind 9, stack 9 |
MVI | 0280-0287 direct0288-02AF indirect02B0-02B7 stack (PULR)02B8-02BF immediate (MVII) | Move in: memory is loaded into the register. MVI $0200, R0, MVI@ R4, R0, MVII #$0123, R0. | none | dir 10, imm 8, ind 8, stack 11 |
ADD | 02C0-02C7 direct02C8-02EF indirect02F0-02F7 stack02F8-02FF immediate (ADDI) | Add memory to the register. | S Z O C | dir 10, imm 8, ind 8, stack 11 |
SUB | 0300-0307 direct0308-032F indirect0330-0337 stack0338-033F immediate (SUBI) | Subtract memory from the register. | S Z O C | dir 10, imm 8, ind 8, stack 11 |
CMP | 0340-0347 direct0348-036F indirect0370-0377 stack0378-037F immediate (CMPI) | Compare: the register minus memory; the result is not stored. | S Z O C | dir 10, imm 8, ind 8, stack 11 |
AND | 0380-0387 direct0388-03AF indirect03B0-03B7 stack03B8-03BF immediate (ANDI) | AND memory into the register. | S Z | dir 10, imm 8, ind 8, stack 11 |
XOR | 03C0-03C7 direct03C8-03EF indirect03F0-03F7 stack03F8-03FF immediate (XORI) | Exclusive OR memory into the register. | S Z | dir 10, imm 8, ind 8, stack 11 |
PSHR | 0270-0277 | Alias: MVO@ of a register through R6: push it on the stack. | none | 9 |
PULR | 02B0-02B7 | Alias: MVI@ through R6 into a register: pull it from the stack. | none | 11 |
Not described
Known, not yet covered
- Reference: cycle counts with SDBD, and the cycle effect of memory wait states.
Unknown
- Reference: flags of the rotates and shifts through the carry for a one-position shift (whether O changes); the page lists S Z O C as the wiki does.
- Reference: whether MVI sets S and Z (both sources say it does not).