Introduction
The CP1610 has eight 16-bit registers and a four-bit status word. Memory is addressed in 16-bit words (a ROM or RAM that is only eight or ten bits wide is read with the high bits zero). This page follows jzIntv’s documentation of the processor.
The registers
| Register | Role |
|---|---|
R0 | General purpose. It cannot be used as a data counter: the indirect-mode code for R0 is the direct mode. |
R1, R2, R3 | General purpose and data counters: an indirect access through one reads or writes the memory it points to and leaves it unchanged. |
R4, R5 | Data counters that increase after every access through them (twice with SDBD). JSR saves the return address in R4, R5 or R6. |
R6 | The stack pointer: it increases after a write (push) and decreases before a read (pull), so the stack grows upward. PSHR and PULR use it. |
R7 | The program counter. Most instructions can use it as a source or destination (JR is a move to it); an immediate operand is a read through it. When an instruction uses R7, it holds the address just after the instruction. |
The status word
| Bit | Flag | Meaning |
|---|---|---|
| 3 | S | Sign: the result’s bit 15 (for shifts of a byte, the byte’s bit 7 after SWAP by 2). |
| 2 | Z | Zero: the result is zero. |
| 1 | O | Overflow. The rotates and shifts through the carry use it to catch the second bit in a two-position shift. |
| 0 | C | Carry (for subtraction and comparison, the carry is set when no borrow was needed). |
GSWD stores the flags into the upper four bits of each byte of a register (R0 to R3 only): bits 15 to 12 and bits 7 to 4 both hold S Z O C. RSWD loads the flags from bits 7 to 4 of a register. CLRC and SETC change the carry alone. The branch conditions are on the instruction page.
Interrupts
The interrupt system is enabled by EIS (and JE, JSRE) and disabled by DIS (JD, JSRD). When an interrupt is taken, the processor pushes the program counter on the stack (R6) and jumps to an address provided by external hardware; the Intellivision’s EXEC ROM provides $1004. TCI terminates the current interrupt. Interrupts are taken after an instruction that is interruptible (the shifts and rotates, the stores, EIS, DIS, SDBD, TCI, CLRC and SETC are not) and not after one directly following a non-interruptible one. HLT stops the processor. The instruction pages say which instructions are not interruptible.
Not described
Known, not yet covered
- Reference: the reset vector and the interrupt vector of other systems, the PCIT pin and SIN, the four external condition pins and how a system connects them (on the Intellivision they are not connected).
Unknown
- Reference: what HLT does exactly ("until the next interrupt", the documentation says with a question mark).