Introduction
Bits here are numbered from the least significant bit (bit 0) of the ten-bit decle. The first decle of an instruction holds the opcode and its register and mode fields; a following decle (or two) holds an address, a displacement or an immediate value.
Decles
The processor’s instructions and data are 10 bits wide in the original ROMs; each is a decle. A ROM file (the .bin of an Intellivision cartridge) stores a decle in a 16-bit big-endian word, high byte first, with the top six bits zero. An address counts decles from the load address: the decle at byte offset n has the address base + n / 2. A listing drawn byte by byte shows a byte at an odd offset as the second half of a decle (the status Odd address). The explorer decodes a decle with only its low ten bits and marks an instruction whose top six bits are not zero as Undocumented.
The opcode formats
| Bits 9 to 0 | Decles | Instructions |
|---|---|---|
0000 000 0oo and 0000 000 1oo | 1 | HLT SDBD EIS DIS (o = 0 to 3); TCI CLRC SETC (o = 1 to 3 of the second group) |
0000 000 100 + bbppppppii + pppppppppp | 3 | The jumps: bb is the return register (R4, R5, R6, 3 = none), ii the interrupt mode (0 no change, 1 enable, 2 disable, 3 reserved), the target is the 6 + 10 bits p. |
0000 ooo ddd | 1 | INCR DECR COMR NEGR ADCR RSWD (o = 1, 2, 3, 4, 5, 7); GSWD and NOP/SIN use 0000 110 0dd and 0000 110 1om |
0001 ooo mrr | 1 | SWAP SLL RLC SLLC SLR SAR RRC SARC on R0 to R3; m = 1 shifts twice |
0ooo sss ddd | 1 | MOVR ADDR SUBR CMPR ANDR XORR (o = 2 to 7): source register, destination register |
1000 zxc ccc + one decle | 2 | The branches: z = backward, x = external condition, the low four bits the condition (bit 3 negates) or the external line |
1ooo mmm rrr (+ one decle when m is 0 or 7) | 1 to 2 (3 with SDBD) | MVO MVI ADD SUB CMP AND XOR (o = 1 to 7): the mode m and the register r |
The memory modes
| m | Mode | Written | Meaning |
|---|---|---|---|
| 0 | Direct | MVI $0200, R1 | The next decle is the address. The register is the source of MVO and the destination of the rest. |
| 1 to 3 | Indirect | MVI@ R2, R1 | The memory at the address in R1, R2 or R3 (m is the pointer register). |
| 4, 5 | Indirect with auto-increment | MVI@ R4, R1 | The same through R4 or R5, which then increase by one. |
| 6 | Stack | PULR R1, PSHR R1 | Through R6: a store increases it afterwards (push), a load decreases it first (pull). The assembler names are PSHR and PULR. |
| 7 | Immediate | MVII #$0002, R1 | Through R7: the decle that follows is the value (a read), or what MVOI overwrites. |
The mnemonic gets an @ for the indirect and stack forms (MVI@, ADD@, …) and an I for the immediate form (MVII, ADDI, …).
Branch targets
A branch is two decles; the second is an unsigned displacement. Forward (z = 0): target = address of the branch + 2 + displacement. Backward (z = 1): target = address of the branch + 1 − displacement. The jumps (J, JSR…) carry the full 16-bit address in two decles: the upper six bits in bits 7 to 2 of the second decle, the lower ten in the third.
SDBD
SDBD (set double byte data, decle 1) is a prefix: it affects only the next instruction. It exists for 8-bit-wide memory that holds 16-bit values as two bytes, low byte first. After SDBD:
- an immediate instruction (MVII, ADDI, …) has two data decles, the low byte in the first and the high byte in the second, each only 8 bits: the instruction is three decles long and the value is 16 bits;
- an indirect instruction (MVI@, ADD@, …) makes two memory accesses, low byte first; R4 and R5 increase twice, R1 to R3 do not change, and the instruction stays one decle;
- any other instruction is not changed. jzIntv’s dis1600 marks SDBD as illegal before a direct address, before a store (MVO@, MVOI) or before a stack access; its emulator core decodes MVOI after SDBD as three decles and its simple disassembler dasm1600 as two. The explorer shows these as Undocumented with the core’s length.
The disassembler shows SDBD as an instruction of its own and then the next instruction in its SDBD form; the decoder is told the previous decle was SDBD.
Not described
Known, not yet covered
- Reference: the 8-bit packed ROM formats (two decles per three bytes) of some ROM images.
Unknown
- Reference: the effect of SDBD before the instructions it should not precede, as above.
Links
Reference
- jzIntv – doc/jzintv/cp_1610.txt describes the formats, the SDBD notes and the branch offsets