ARM64 instruction set reference

Introduction

A64 is the instruction set of AArch64, the 64-bit execution state that Arm introduced with Armv8-A. ARM64 is its everyday name.

Every A64 instruction is one 32-bit word, and instructions are always stored little-endian. There are no shorter or longer forms, so code can be read from any multiple of four bytes. Data can also be big-endian on a processor that supports it, but almost every system uses little-endian data too.

There are 31 general registers, x0 to x30, each 64 bits wide. w0 to w30 are their low 32 bits. Register number 31 is not a 32nd general register: depending on the instruction, it means the stack pointer, sp, or the zero register, xzr or wzr, which reads as zero and ignores writes. The program counter is not a general register.

Four condition flags, N, Z, C and V, record the result of a comparison or a calculation. Most arithmetic leaves them alone. Only the forms that say so set them, such as adds, subs and ands. Conditional branches and conditional selects read them. The Registers page describes all of these, with the floating-point, SIMD, SVE and SME registers.

Fileformats.org’s explorer disassembles the ARM64 code in Mach-O programs and in COFF object files, with its text in the form that LLVM prints.

How this reference is organised

Two pages explain how instructions are put together. The other pages each cover one group of instructions. A group page has one table for each kind of instruction, with the mnemonic, its syntax as the disassembler prints it, what it does and which flags it sets. The explorer links each instruction it shows to its row.

• Instruction encoding – how a 32-bit word divides into groups and fields, the immediates, PC-relative targets and conditions
• Registers – the general, flag, floating-point, SIMD, SVE and SME registers
• Integer data processing – arithmetic, logic, shifts, bitfields, multiplication, division and conditional selection
• Branches and exceptions – branches, calls and returns, and the instructions that raise and return from exceptions
• Loads and stores – single and paired loads and stores, load-acquire and store-release, exclusive access and prefetch
• Atomic and exclusive access – compare and swap, swap, atomic read-modify-write, and 64-byte loads and stores
• Pointer authentication – signing, checking and stripping pointers
• Memory tagging – setting and checking the tags on addresses and memory
• Memory copy and set – the instruction sequences that copy and fill memory
• System instructions – system registers, barriers, hints, cache operations and the guarded control stack
• Floating point – scalar floating-point arithmetic, comparison and conversion
• Advanced SIMD (NEON) – integer and floating-point operations on the 64-bit and 128-bit vector registers
• Advanced SIMD loads and stores – loading and storing vectors, single elements and interleaved structures
• Cryptography – AES, SHA-1, SHA-2, SHA-3, SM3 and SM4
• SVE – the Scalable Vector Extension, with its scalable vectors and predicates
• SVE2 and later – the instructions SVE2 and its later versions add
• SME – the Scalable Matrix Extension and its two-dimensional ZA storage
• SME2 and later – the instructions SME2 and its later versions add

Links