ARM64 Instruction Set – Advanced SIMD loads and stores

Introduction

These instructions move elements between memory and a list of vector registers. The number in the mnemonic is the number of elements in one structure, from 1 to 4. An RGB pixel is a structure of three bytes, so ld3 reads a run of them and puts the reds in one register, the greens in the next and the blues in the third.

The register list is written in braces. Its registers are numbered in order, and the numbering wraps from V31 to V0. The base address is X0 to X30 or SP.

There are three shapes of operation:

Multiple structures fill or store whole registers: ld2 { v0.8b, v1.8b }, [x0].
A single structure transfers one element of each register, and leaves the other elements alone: ld2 { v0.b, v1.b }[3], [x0].
Replicating loads read one structure and copy it to every element: ld2r { v0.8b, v1.8b }, [x0].

Most forms can also write back to the base register afterwards. The post-index form adds either the size of the transfer as an immediate, [x0], #16, or a register, [x0], x1. ldap1 and stl1 have no write-back form.

A load into a 64-bit vector, such as .8b, clears the top half of the register. None of these instructions changes NZCV. Ordinary whole-register loads and stores such as ldr q0 are on the Loads and stores page.

The instructions

Loading structures

Mnemonic	Syntax	What it does	Flags
`ld1`	`ld1 { Vt.8b }, [Xn]`; `ld1 { Vt.b }[i], [Xn]`	Loads whole registers with no interleaving, using one to four consecutive registers; or loads one element into a lane.	–
`ld2`, `ld3`, `ld4`	`ld2 { Vt.8b, Vt2.8b }, [Xn]`; `ld2 { Vt.b, Vt2.b }[i], [Xn]`	Loads two, three or four interleaved elements per structure and de-interleaves them across that many registers; or loads one structure into a lane of each register. The multiple-structure forms have no `.1d` arrangement.	–
`ld1r`, `ld2r`, `ld3r`, `ld4r`	`ld1r { Vt.8b }, [Xn]`	Loads one structure and copies each of its elements to every lane of its own register.	–

Storing structures

Mnemonic	Syntax	What it does	Flags
`st1`	`st1 { Vt.8b }, [Xn]`; `st1 { Vt.b }[i], [Xn]`	Stores whole registers with no interleaving, using one to four consecutive registers; or stores one lane.	–
`st2`, `st3`, `st4`	`st2 { Vt.8b, Vt2.8b }, [Xn]`; `st2 { Vt.b, Vt2.b }[i], [Xn]`	Interleaves two, three or four registers into memory; or stores one structure from a lane of each register. The multiple-structure forms have no `.1d` arrangement.	–

Ordered lane access

These two come with the RCpc 3 extension (FEAT_LRCPC3). They transfer one 64-bit lane, take a base register with no offset and have no write-back.

Mnemonic	Syntax	What it does	Flags
`ldap1`	`ldap1 { Vt.d }[i], [Xn]`	Loads a doubleword into one lane with load-acquire (RCpc) ordering. The other lanes are unchanged.	–
`stl1`	`stl1 { Vt.d }[i], [Xn]`	Stores one doubleword lane with store-release ordering.	–