ARM64 Instruction Set – Registers

Introduction

This page describes the registers that A64 instructions name: the general registers, the condition flags, the floating-point and SIMD registers, the SVE and SME registers and, in general terms, the system registers.

The roles given to the general registers below come from Arm’s procedure-call standard for 64-bit code, AAPCS64. The architecture itself gives special treatment only to a few of them. Compilers and operating systems follow the standard, with some platform differences.

General registers

There are 31 general registers of 64 bits, x0 to x30. w0 to w30 are the low 32 bits of the same registers. An instruction that writes a w register clears the top 32 bits of the x register.

A caller-saved register may be changed by a function that is called, so a caller that needs its value must keep a copy. A callee-saved register must have the same value when the function returns.

Register number 31

The register fields are five bits, and number 31 has no x31. It means sp or the zero register, depending on the field. For example:

• The base register of a load or store: sp.
• The register a load or store transfers: xzr or wzr.
• add and sub with an immediate: sp, for both source and destination.
• adds and subs with an immediate: sp for the source and the zero register for the destination.
• The shifted-register forms of add, sub and the logical instructions: the zero register.

The program counter is not one of the general registers. Code reaches it only through PC-relative instructions and branches.

Condition flags

The condition flags are part of PSTATE, the processor’s state. There are four:

Only some instructions set the flags: the forms ending in s, such as adds and ands, and instructions such as ccmp and fcmp. The group pages give the flags each instruction sets. The condition field reads them. mrs and msr can also read and write them, as the NZCV system register.

Floating-point and SIMD registers

There are 32 registers, v0 to v31, each of 128 bits. They are separate from the general registers, and hold floating-point values, integers and vectors. Each has narrower views, which all start at bit 0:

An instruction that writes a scalar view, or a 64-bit vector, clears the rest of the register.

A vector operand has an element suffix that gives the number and size of its elements:

One element is written with an index, as in v1.s[2].

In the procedure-call standard, v0–v7 hold arguments and results. v8–v15 are callee-saved, but only their low 64 bits. The others are caller-saved.

The system registers FPCR and FPSR hold floating-point control settings and status.

SVE registers

The Scalable Vector Extension widens the vector registers. z0 to z31 are the same registers as v0 to v31, and the v register is the low 128 bits of the z register. Their length depends on the processor, between 128 and 2048 bits, and code can be written to work at any length.

p0 to p15 are predicate registers, with one bit for each byte of a z register. A predicate chooses which elements an instruction acts on. There is also a first-fault register, ffr, which records which elements of a first-fault load succeeded.

Element sizes are written .b, .h, .s and .d, and .q on a few instructions. An SVE operand gives only the element size, because the number of elements depends on the vector length: z0.s.

Where an instruction takes a governing predicate, p0/m merges (inactive elements of the destination are kept) and p0/z zeroes (inactive elements become zero).

Under the procedure-call standard, scalable vectors are passed in z0–z7 and predicates in p0–p3. A function that takes or returns them must preserve z8–z23 and p4–p15.

SME registers

The Scalable Matrix Extension adds za, a two-dimensional array of bytes. It is square, with as many rows and columns as there are bytes in a streaming SVE vector. A processor enters streaming SVE mode and enables ZA with smstart, and leaves with smstop.

ZA is addressed as tiles, whose number depends on the element size:

A tile is also read and written one slice at a time, horizontally or vertically. za0h.s[w12, 0] is the horizontal slice of tile za0.s at index w12 + 0, and za0v.s names vertical slices.

SME2 adds zt0, a 512-bit register that holds a lookup table.

System registers

System registers hold configuration and status, and there are hundreds of them. They are not named as operands in ordinary instructions. mrs reads one into a general register, and msr writes one. Many are only accessible at a higher exception level. A name often ends in the lowest exception level that can use it, as in TPIDR_EL0 and SCTLR_EL1.

Each system register is identified by five numbers, called op0, op1, CRn, CRm and op2, which the instruction encodes. The System instructions page describes mrs, msr and the related instructions.

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