MSP430 Instruction Set – Overview

Texas Instruments’ 16-bit microcontroller and its 20-bit extension

Introduction

The MSP430 is Texas Instruments’ 16-bit, low-power microcontroller family (1992): the chip of the LaunchPad boards (MSP430G2553 and its relatives), of electricity meters, and of many battery devices. It has 16 registers, a single 64 KB address space for code, data and peripherals, 27 core instructions of three formats, and an unusually regular set of addressing modes in which two of the registers double as the constant generators. The larger devices use the MSP430X CPU (CPUX): 20-bit registers and addresses, and an extension word that widens an instruction.

These pages describe the instruction set and the disassembler the explorer uses for it (explorer/cpu/msp430/, our own code), which reads the code of an ELF file for the MSP430 (machine type 105) and of an Intel HEX file (the form the TI tools write).

Statuses

  • documented: an instruction of the CPU chosen;
  • reserved: no instruction has this encoding on the CPU chosen (for the 16-bit CPU that includes the whole MSP430X range, 0x0000 to 0x0FFF and the extension words 0x1800 to 0x1FFF). The disassembly shows .word and the instruction is two bytes long.

What the viewer lets you choose

  • CPU: MSP430 (16-bit) or MSP430X. In an ELF file the default is read from .MSP430.attributes (the ISA tag); a HEX file does not say.
  • Emulated instructions (the default): ret, nop, pop r5, br r5, clr, inc, eint … or the core instruction as encoded (mov @r1+, r0). Emulated instructions lists them.

How this was checked

  • llvm, the 16-bit CPU. All 65,536 first words, each with operand words that are invalid when unused (so the number of words used shows), then every word that takes operand words again with four other operand-word patterns (negative offsets, 0xFFFF, 0x8000): 185,644 comparisons with llvm-mc --disassemble --triple=msp430, no unexplained difference. About 1,300 words differ and each belongs to a listed llvm gap or quirk: llvm rejects @PC as a source, PUSH with an indexed, absolute or symbolic operand, PUSH.B of constants and indirect operands, MOV @Rn+ to memory, the constant #1 as the operand of a one-operand instruction and an immediate operand of RRC and the like; it writes PUSH @Rn as a constant; and it writes BR and POP only for some operand forms. The test file lists each class.
  • An emulator. The MSP430 core of the LaunchPad emulator on emulators.org ran every word the decoder calls documented, from random states: the program counter, the registers and the flags it changes, and (by changing one register at a time) the registers it reads: 166,893 executions and 298,909 read checks, no difference. (That core counts one cycle for every instruction, so it is no check of the cycle counts.)
  • Real programs. A program built with clang for the MSP430 and linked with lld, and the object file of the ELF fixtures, compared instruction by instruction with llvm-objdump in the ELF viewer (71 instructions).
  • MSP430X has no llvm check: llvm cannot decode the extension word or the address instructions at all (every one is “invalid” to it). Their encodings were written from TI’s MSP430x5xx/MSP430FR5xx user’s guide (SLAU208 / SLAU367, the CPUX chapter, read online) and from the GNU binutils decoder’s opcode patterns, read online; the decoder is checked against its own table of those encodings only. No MSP430X program or emulator was available on the machine.

Sources

Not described

  • Cycle counts: only the register-destination forms of the 16-bit core are tabulated by the viewer (and the one-operand and jump instructions); the memory and PC destinations and all MSP430X counts are in the manuals.
  • The hardware multiplier, the peripherals, interrupt vectors and the bootloader; the reset vector at 0xFFFE is the only vector the viewer knows of, and does not name.
  • The effect of the SCG and CPUOFF status bits (low-power modes), beyond saying that an instruction writes SR.
  • MSP430X: see its page for what is not covered.