The sixteen registers
| Register | Name | Use |
|---|---|---|
R0 | PC | Program counter. Always even: an instruction is one to three words (four on the MSP430X), starting at an even address. Instructions that write R0 jump. |
R1 | SP | Stack pointer. Always even; the stack grows toward lower addresses (PUSH decrements it by two, then stores). |
R2 | SR, CG1 | Status register, and the first constant generator: in some addressing modes it supplies the constants 4 and 8 or the absolute-address mode instead of its value. |
R3 | CG2 | The second constant generator: it never holds a value, only the constants 0, 1, 2 and −1 (all ones). Writing it has no effect. |
R4 to R15 | General purpose, 16 bits (20 bits on the MSP430X). |
The disassembler writes the registers by number (r0 to r15), as llvm does; TI’s tools write PC, SP, SR and CG for the first four.
The status register
| Bit | Flag | Meaning |
|---|---|---|
| 8 | V | Overflow |
| 7 | SCG1 | System clock generator 1 off (low-power mode) |
| 6 | SCG0 | System clock generator 0 off |
| 5 | OSCOFF | Oscillator off |
| 4 | CPUOFF | CPU off (low-power mode) |
| 3 | GIE | General interrupt enable (EINT sets it, DINT clears it) |
| 2 | N | Negative |
| 1 | Z | Zero |
| 0 | C | Carry |
The viewer lists the flags V, N, Z and C that an instruction changes or reads. BIC and BIS with SR as the destination (the emulated EINT, DINT, CLRC, SETC …) change the others; so does MOV to SR.
Memory
The MSP430 has one address space: peripherals at the bottom (0x0000 to 0x01FF on the 2xx devices), then RAM, then flash at the top, with the interrupt vectors in the last 32 bytes and the
reset vector at 0xFFFE. There is no separate I/O space and no I/O instruction: peripherals are read and written like memory (with .B for the byte-wide ones). Words are stored
little-endian at even addresses; a word access at an odd address ignores the low bit of the address. The 16-bit CPU reaches 64 KB; the MSP430X reaches 1 MB with 20-bit addresses.
Every instruction operates on bytes (.B) or words (the default, written .W in TI’s listings). A byte operation on a register clears the upper byte of the destination.
Not described
- The memory map of a particular device and its peripheral registers (which differ by family: 2xx, 4xx, 5xx, FRxx).
- Interrupt handling (the CPU pushes PC and SR and clears most of SR), the low-power modes and the reset sequence.