MSP430 Instruction Set: MSP430X

How well this is checked

Nothing on this page was compared with a second implementation. llvm cannot decode the MSP430X (the extension word and every address instruction are “invalid” to it), no MSP430X emulator or toolchain was available, and no MSP430X program was on the machine. The bit patterns were taken from TI’s user’s guide (SLAU208 / SLAU367, the CPUX chapter) and from the opcode patterns of the GNU binutils decoder, both read online, and the decoder is tested against its own table of them only. Treat the details of the extension word (the repeat count, the zero-carry bit) as less certain than the rest of these pages.

What the MSP430X adds

20-bit registers (R0 to R15) and addresses: a 1 MB address space. PC and SP are 20 bits; the instructions without an extension word still work on 16 bits and clear the upper four bits of a register they write.
The extension word: a word in front of a core instruction that makes it a 20-bit (.A), 16-bit (.W) or 8-bit (.B) operation with 20-bit offsets and addresses, or makes it repeat.
Address instructions that always work on 20 bits (MOVA, CMPA, ADDA, SUBA), multi-bit shifts, PUSHM and POPM, and CALLA.

The extension word

An extension word is any word from 0x1800 to 0x1FFF (0001 1 in bits 15 to 11) followed by a core instruction of format I or II. It comes in two forms, chosen by the instruction that follows: when every operand is in register mode it is the register-mode form; otherwise the non-register form.

Bits	Register-mode form	Non-register form
15 to 11	`00011`
10 to 9	0 (reserved)	bits 19 to 16 of the source operand’s offset, address or immediate (bits 10 to 7)
8	`ZC`: 1 = the carry is not used (taken as zero) by `ADDC`, `SUBC`, `DADD` and the rotates
7	`#`: 0 = the repeat count is in bits 3 to 0, 1 = it is in the low four bits of the register named there	(bit 7 of the source bits above)
6	`A/L`, which together with the instruction’s B/W bit gives the size: A/L = 0 and B/W = 1: 20 bits (`.A`); A/L = 1 and B/W = 0: 16 bits (`.W`); A/L = 1 and B/W = 1: 8 bits (`.B`); A/L = 0 and B/W = 0: reserved
5 to 4	0 (reserved)
3 to 0	the repeat count minus one, or the register that holds it	bits 19 to 16 of the destination operand’s offset or address

With the extension word the instruction gets an x in its name: movx.a, addx.w, rrax.a, pushx.b. The extra words that hold offsets, absolute addresses and immediates are the same as before, with the 16 bits that follow and the four bits from the extension word making 20. The repeat is written rpt #n { rrax.a r5 (or rpt r6 { … for a count in a register).

There is no extended CALL (CALLA is the 20-bit call); the extended instructions are in the table below, one anchor each.

Core instruction	Extended	Notes
`MOV`	`MOVX.A`, `.W`, `.B`
`ADD`	`ADDX`
`ADDC`	`ADDCX`	ZC applies in register mode.
`SUBC`	`SUBCX`	ZC applies in register mode.
`SUB`	`SUBX`
`CMP`	`CMPX`
`DADD`	`DADDX`	ZC applies in register mode.
`BIT`	`BITX`
`BIC`	`BICX`
`BIS`	`BISX`
`XOR`	`XORX`
`AND`	`ANDX`
`RRC`	`RRCX`	The repeat count applies in register mode.
`RRA`	`RRAX`	The repeat count applies in register mode.
`SWPB`	`SWPBX`	.A swaps the bytes of the low word of a 20-bit value.
`SXT`	`SXTX`	.A sign-extends bit 7 into bits 8 to 19.
`PUSH`	`PUSHX`	.A pushes 20 bits in two words.

The address instructions

The words 0x0000 to 0x0FFF, which are no instruction on the 16-bit CPU. They need no extension word and work on 20 bits. In the patterns sss is the source register, ddd the destination register, and x bits 19 to 16 of an address or immediate whose low 16 bits follow in the next word.

Instruction	Pattern (bits 15 to 0)	Words
`MOVA @Rs,Rd`	`0000 ssss 0000 dddd`	1
`MOVA @Rs+,Rd`	`0000 ssss 0001 dddd`	1
`MOVA &abs20,Rd`	`0000 xxxx 0010 dddd` + low 16 bits	2
`MOVA x(Rs),Rd`	`0000 ssss 0011 dddd` + signed 16-bit offset	2
`MOVA Rs,&abs20`	`0000 ssss 0110 xxxx` + low 16 bits	2
`MOVA Rs,x(Rd)`	`0000 ssss 0111 dddd` + signed 16-bit offset	2
`MOVA #imm20,Rd`	`0000 xxxx 1000 dddd` + low 16 bits	2
`CMPA #imm20,Rd`	`0000 xxxx 1001 dddd` + low 16 bits	2
`ADDA #imm20,Rd`	`0000 xxxx 1010 dddd` + low 16 bits	2
`SUBA #imm20,Rd`	`0000 xxxx 1011 dddd` + low 16 bits	2
`MOVA Rs,Rd`	`0000 ssss 1100 dddd`	1
`CMPA Rs,Rd`	`0000 ssss 1101 dddd`	1
`ADDA Rs,Rd`	`0000 ssss 1110 dddd`	1
`SUBA Rs,Rd`	`0000 ssss 1111 dddd`	1

MOVA does not change flags; CMPA, ADDA and SUBA set V, N, Z and C on the 20-bit result.

Rotates and shifts by several bits

0000 nn kk 010w dddd: nn (bits 11 to 10) is the shift count minus one (1 to 4), kk (bits 9 to 8) the kind, w (bit 4) is 1 for .W (16 bits) and 0 for .A (20 bits), and dddd the register. They set V, N, Z and C.

`kk`	Instruction	Operation
00	`RRCM.A`, `.W #n,Rd`	Rotate right through the carry n times.
01	`RRAM`	Arithmetic shift right n times.
10	`RLAM`	Shift left n times.
11	`RRUM`	Logical shift right n times (zeros into the top bit).

PUSHM, POPM and CALLA

Instruction	Pattern	Operation
`PUSHM.A`, `.W #n,Rd`	`0001 010w nnnn dddd`	Pushes n registers (n = field + 1, 1 to 16), Rd first and then the registers below it, as 20-bit (`.A`, `w` = 0) or 16-bit (`.W`, `w` = 1) values.
`POPM.A`, `.W #n,Rd`	`0001 011w nnnn dddd`	Pops n registers into Rd−n+1 up to Rd.
`CALLA`	`0001 0011 01as dddd` (register, `x(Rn)`, `@Rn`, `@Rn+`), `0001 0011 1000 xxxx` (`&abs20`), `1001` (symbolic), `1011` (`#imm20`), each of the last three followed by the low 16 bits	Pushes the 20-bit return address (two words) and jumps to the 20-bit operand. `CALLA` with `0001 0011 1010` is not an instruction.

RETI on the 20-bit CPU pops SR together with the upper four bits of PC, then PC, and takes more cycles; its encoding is that of the 16-bit CPU.

Not described

Cycle counts of every MSP430X form.
What happens to the upper four bits of a register in each 16-bit operation, and how the repeat count interacts with the flags beyond the manual’s tables.
The bit that marks the extension word’s register-mode form (bits 10 to 9) as reserved: the decoder rejects an extension word with bits 5 or 4 set, and does not check bits 10 to 9.
The emulated X forms: aliases are not applied to the extended instructions.

MSP430 Instruction Set – MSP430X