6800 Instruction Set – 6800, 6801 and 6303

The Motorola MC6800 family and Hitachi’s CMOS versions

The processors

The Motorola MC6800 (1974) is the ancestor of the 6809. The MC6802 and MC6808 are the same instruction set (the 6802 adds 128 bytes of RAM and a clock, the 6808 only the clock). The MC6801 and its ROM-less MC6803 add instructions, among them a hardware multiply. Hitachi’s CMOS HD6301 and HD6303 run the 6801 set plus six more (XGDX, SLP and four read-modify-write instructions with an immediate byte) and trap on undefined opcodes. The viewer’s Processor choice offers these three sets: MC6800, MC6801 and HD6303 (HD6301 and HD6303 decode identically). Programs are not binary-compatible with the 6809. The 6805, 68HC11 and 6811 are not decoded.

Statuses in the viewer: documented for an opcode in the chosen chip’s data sheet; illegal for every other opcode, shown as one .byte (the HD6303 traps through the vector at $FFEE; what the MC6800 and MC6801 do with them is not described here — some are known to halt the MC6800, but no source was read).

Registers, flags and addressing

RegisterSizeUse
A, B8Accumulators; on the 6801 and later together D (A high)
X16The one index register
SP, PC16Stack pointer (it points at the next free byte, and pushes decrement it) and program counter
CC8Condition codes H I N Z V C in bits 5 to 0 (bits 7 and 6 read as 1)

Addressing: immediate #$12 or #$1234; direct $12 (page zero: the high byte is always 0, there is no direct page register); extended $1234; indexed $12,x (the offset is an unsigned byte, 0 to 255, added to X); relative bra $2010 (signed 8-bit); inherent. JMP and JSR have indexed and extended forms (JSR direct from the 6801). Words are big-endian. The 6800 spells the accumulator forms with the letter after the operation (ldaa, staa, oraa, adda, suba…, negb). asl and lsl are the same opcode.

Interrupt vectors: $FFF8 IRQ, $FFFA SWI, $FFFC NMI, $FFFE RESET. $FFEE is the HD6303’s illegal-opcode trap.

Instructions

Opcodes are in hex; a row with several gives them in the order accumulator A, accumulator B (where the instruction has both) or immediate, direct, indexed, extended. Set: 6800 (all four chips), 6801 (MC6801 and later) or 6303 (HD6301 and HD6303 only). Cycles are the MC6800 data sheet’s; the 6801 and 6303 counts differ and are not given. Flags are those the instruction changes.

MnemonicSetOpcodesBytesCycles (6800)FlagsWhat it does
NOP68000112–No operation
TAP68000612H I N Z V CA to CC
TPA68000712–CC to A
INX68000814ZIncrement X
DEX68000914ZDecrement X
CLV68000A12VClear overflow
SEV68000B12VSet overflow
CLC68000C12CClear carry
SEC68000D12CSet carry
CLI68000E12IEnable interrupts
SEI68000F12IMask interrupts
SBA68001012N Z V CA = A − B
CBA68001112N Z V CCompare A with B
TAB68001612N Z VB = A
TBA68001712N Z VA = B
DAA68001912N Z V CDecimal adjust A
ABA68001B12H N Z V CA = A + B
LSRD6801041–N Z V CShift D right
ASLD (LSLD)6801051–N Z V CShift D left
XGDX6303181––Exchange D and X
SLP63031A1––Sleep until an interrupt
BRA68002024–Branch always
BRN6801212––Branch never
BHI68002224–Higher (C and Z clear)
BLS68002324–Lower or same
BCC68002424–Carry clear
BCS68002524–Carry set
BNE68002624–Not equal
BEQ68002724–Equal
BVC68002824–Overflow clear
BVS68002924–Overflow set
BPL68002A24–Plus
BMI68002B24–Minus
BGE68002C24–Greater or equal (signed)
BLT68002D24–Less than (signed)
BGT68002E24–Greater than (signed)
BLE68002F24–Less or equal (signed)
TSX68003014–X = SP + 1
INS68003114–Increment SP
PULA68003214–Pull A
PULB68003314–Pull B
DES68003414–Decrement SP
TXS68003514–SP = X − 1
PSHA68003614–Push A
PSHB68003714–Push B
PULX6801381––Pull X
RTS68003915–Return from subroutine
ABX68013A1––X = X + B (unsigned)
RTI68003B110H I N Z V CReturn from interrupt
PSHX68013C1––Push X
MUL68013D1–CD = A × B, unsigned
WAI68003E19–Push the state and wait for an interrupt
SWI68003F112ISoftware interrupt through $FFFA
NEG NEGA NEGB680060 70 · 40 · 502 3 · 17 6 · 2N Z V CTwo’s complement
COM …680063 73 · 43 · 532 3 · 17 6 · 2N Z V COne’s complement
LSR …680064 74 · 44 · 542 3 · 17 6 · 2N Z V CLogical shift right
ROR …680066 76 · 46 · 562 3 · 17 6 · 2N Z V CRotate right through carry
ASR …680067 77 · 47 · 572 3 · 17 6 · 2N Z V CArithmetic shift right
ASL …680068 78 · 48 · 582 3 · 17 6 · 2N Z V CShift left
ROL …680069 79 · 49 · 592 3 · 17 6 · 2N Z V CRotate left through carry
DEC …68006A 7A · 4A · 5A2 3 · 17 6 · 2N Z VDecrement
INC …68006C 7C · 4C · 5C2 3 · 17 6 · 2N Z VIncrement
TST …68006D 7D · 4D · 5D2 3 · 17 6 · 2N Z V C (V and C cleared)Test against zero
CLR …68006F 7F · 4F · 5F2 3 · 17 6 · 2N Z V CClear
JMP68006E 7E2 34 3–Jump
AIM630361 indexed · 71 direct3–N Z VAND an immediate byte into memory: aim #$0f,$40, aim #$0f,$40,x
OIM630362 · 723–N Z VOR an immediate byte into memory
EIM630365 · 753–N Z VExclusive OR an immediate byte into memory
TIM63036B · 7B3–N Z VTest memory against an immediate byte
SUBA SUBB680080 90 A0 B0 · C0 D0 E0 F02 2 2 32 3 5 4N Z V CSubtract
CMPA CMPB680081 91 A1 B1 · C1 D1 E1 F12 2 2 32 3 5 4N Z V CCompare
SBCA SBCB680082 92 A2 B2 · C2 D2 E2 F22 2 2 32 3 5 4N Z V CSubtract with borrow
SUBD680183 93 A3 B33 2 2 3–N Z V CSubtract from D
ANDA ANDB680084 94 A4 B4 · C4 D4 E4 F42 2 2 32 3 5 4N Z VAND
BITA BITB680085 95 A5 B5 · C5 D5 E5 F52 2 2 32 3 5 4N Z VBit test
LDAA LDAB680086 96 A6 B6 · C6 D6 E6 F62 2 2 32 3 5 4N Z VLoad accumulator
STAA STAB680097 A7 B7 · D7 E7 F72 2 34 6 5N Z VStore accumulator
EORA EORB680088 98 A8 B8 · C8 D8 E8 F82 2 2 32 3 5 4N Z VExclusive OR
ADCA ADCB680089 99 A9 B9 · C9 D9 E9 F92 2 2 32 3 5 4H N Z V CAdd with carry
ORAA ORAB68008A 9A AA BA · CA DA EA FA2 2 2 32 3 5 4N Z VOR
ADDA ADDB68008B 9B AB BB · CB DB EB FB2 2 2 32 3 5 4H N Z V CAdd
ADDD6801C3 D3 E3 F33 2 2 3–N Z V CAdd to D
CPX68008C 9C AC BC3 2 2 33 4 6 5N Z VCompare X with memory (the HD6303 also changes C: see the checks)
BSR68008D28–Branch to subroutine
LDS68008E 9E AE BE3 2 2 33 4 6 5N Z VLoad the stack pointer
STS68009F AF BF2 2 35 7 6N Z VStore the stack pointer
JSR6800 (direct: 6801)AD BD · direct 9D2 38 9–Jump to subroutine
LDD6801CC DC EC FC3 2 2 3–N Z VLoad D
STD6801DD ED FD2 2 3–N Z VStore D
LDX6800CE DE EE FE3 2 2 33 4 6 5N Z VLoad X
STX6800DF EF FF2 2 35 7 6N Z VStore X

How this was checked

  • The MC6800 decoder’s opcodes, lengths, registers, flags, memory use, branch targets and cycle counts are compared with the executing core in emulators.org/emulator/williams/src/m6800.js (4,656 executions): no difference, except that this core takes one cycle too few for indexed LDS, STS, LDX and STX (the data sheet says 6, 7, 6, 7).
  • The HD6303 decoder is run against the Psion Organiser II’s HD6303 core (emulators.org/emulator/jape-psion/src/hd6303.js; 5,400 executions) for the whole 6801 and 6303 sets: lengths, registers, flags, memory use; and compared opcode by opcode with the debugger’s own hd6301.js decoder. That core also changes C in CPX, which the MC6800 data sheet does not.

Not described

  • What the MC6800 and MC6801 do with undefined opcodes, the 6801’s cycle counts and the 6801’s on-chip timer and serial registers, the 6802’s RAM, the 6805, 68HC11 and 6811.
  • The HD6303’s TRAP sequence beyond the vector address.