F8 Instruction Set

Introduction

The F8 is Fairchild’s 8-bit microprocessor family (1975), the processor of the Fairchild Video Entertainment System, later called the Channel F (1976), and, as the Mostek 3870, of many single-chip controllers. It is unlike other processors of its time in that the CPU (the 3850) has no address bus: the program counter PC0, its saved copy PC1 and the data pointers DC0 and DC1 live in the memory and port chips (the 3851 program storage unit, the 3852 memory interface), which all follow the CPU’s instructions in lock step. The CPU itself has an 8-bit accumulator A, a 64-byte scratchpad addressed through the six-bit indirect register ISAR, a five-bit status register W and 256 I/O ports.

Instructions are 1, 2 or 3 bytes; the high bits of the opcode are the operation and the low bits often a register or a small value. Of 256 opcodes 253 are instructions; 2D, 2E and 2F are not. Many instructions are one byte because the scratchpad register is in the opcode and the ISAR does the addressing.

The pages: registers, scratchpad and status, every instruction and the opcode map.

Statuses in the disassembly

Notation

Upper-case mnemonics, hexadecimal with $, scratchpad registers as numbers 0 to 11 and the indirect forms S, I and D: LR A,5, AS I, LIS 7, LI $2A, DCI $0800, JMP $0104, OUTS 4, BNZ $0108, BT 3,$0108. A branch shows the address it goes to. The branch names BP, BC, BZ, BM, BNC, BNZ, BNO and BR are masks of BT and BF (see the instruction page); other masks are written BT n,addr and BF n,addr. The plain syntax option writes lower case.

Not described

Known, not yet covered

• Reference: the support chips (3851, 3852, 3853: ports, interval timer, interrupts and the ROMC bus codes that make the processor work), the 3870 and other single-chip F8 parts with their own on-chip RAM, and the Channel F’s memory map and cartridge format (later pages).
• Viewer: every byte is decoded as an instruction; the register values (ISAR, DC0) are not tracked, so a load of DC0 or a scratchpad-indirect access is not followed.

Unknown

• Reference: what register designator 15 does (the sources disagree), what 2D, 2E and 2F do on a real chip, the flag effects of SR, SL, IN and INS and the ADC instruction (the tables read list them inconsistently or not at all), and the exact timing of the support chips.
• Reference: the status flag bit layout of the status register W as read by LR J,W: the one core read stores the sign in bit 0 as negative, the instruction page of the tables read says the sign flag is set when the result is positive.

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