F8 Registers

Introduction

Most of the F8’s state is not in the CPU. The 3850 holds A, ISAR, W and the scratchpad; the program and data addresses are held, identically, by every support chip on the bus.

The registers

Register	Size	Role
`A`	8 bits	The accumulator.
`ISAR`	6 bits	The indirect scratchpad address register: the scratchpad byte the designators S, I and D address. LISU loads its upper three bits, LISL its lower three, LR IS,A loads it all; LR A,IS reads it.
Scratchpad	64 bytes	Registers 0 to 11 can be addressed directly by an instruction; all 64 through the ISAR. Registers 9 to 15 have fixed roles: J (9) is the copy of the status register, H (10 and 11) and Q (14 and 15) hold addresses that LR DC,H / LR H,DC / LR DC,Q / LR Q,DC move to and from DC0, and K (12 and 13) the address used by PK and by LR K,P and LR P,K. KU, KL, QU and QL are 12 to 15 individually.
`PC0`	16 bits	The program counter (in the support chips). A call (PI, PK) saves it in PC1; POP restores it.
`PC1`	16 bits	The one-level return address register: there is only one, so a nested call must save PC1 itself (LR K,P stores it in K).
`DC0`, `DC1`	16 bits	The data counters: DC0 addresses the memory byte of LM, ST, AM, AMD, NM, OM, XM, CM and is increased after each; DCI loads it; XDC exchanges DC0 and DC1; ADC adds A to it.
`W`	5 bits	The status register: the flags below. LR W,J and LR J,W copy it from and to scratchpad register 9.
Ports	256	I/O ports 0 to 255; IN and OUT address any, INS and OUTS ports 0 to 15. Ports 0 to 3 are in the 3850 itself.

Scratchpad register designators

The low four bits of DS, LR A,r, LR r,A, AS, ASD, XS and NS name a scratchpad register:

Value	Written	Meaning
0 to 11	`0` to `11`	The scratchpad register of that number.
12	`S`	The scratchpad register the ISAR points to; the ISAR does not change.
13	`I`	The same; afterwards the low three bits of the ISAR are increased by one (the upper three bits do not change: the count wraps inside a group of eight).
14	`D`	The same; afterwards the low three bits of the ISAR are decreased by one.
15	`15`	Not defined. One description says the instruction is a no-operation; the Channel F core read treats it as S. The explorer decodes it with the status Undocumented.

The status register and the flags

Bit	Flag	Meaning
0	`S`	Sign: set when the result is positive (bit 7 clear). BP (BT 1) branches on it, BM (BF 1) when it is clear.
1	`C`	Carry out of bit 7 (cleared by logical operations and shifts).
2	`Z`	Zero: the result is zero.
3	`O`	Overflow: the signed result does not fit (carry out of bit 7 differs from the carry out of bit 6; cleared by logical operations).
4	`I`	Interrupt enable: EI sets it, DI clears it.

BT tests the flags S, C and Z with a three-bit mask and branches if any selected flag is set; BF tests S, C, Z and O with a four-bit mask and branches if none is set. BR7 branches while the low three bits of the ISAR are not 7: a loop counter over a group of eight scratchpad registers.

Not described

Known, not yet covered

Reference: the interrupt sequence, the interval timer of the 3851 and 3853, and the ROMC lines.

Unknown

Reference: the exact bit layout of W as LR J,W stores it (see the overview), and what LISU/LISL leave in the unused bits.

F8 Instruction Set – Registers, scratchpad and status