F8 Instructions

Introduction

Each row gives the instruction, its opcode (a range is every register, port or value), its length in bytes, its machine cycles (one machine cycle is four clock periods: the short instructions take 1, the longest 6.5; a branch shows the not-taken and the taken count), what it does and the flags it changes (S C Z O, and I for the interrupt enable). r is a scratchpad register designator; DPCHR one of KU, KL, QU, QL. The cycle counts are those of the opcode table read for this work; the one core read disagrees for some instructions, listed in the checks.

Register moves

Instruction	Opcode	Bytes	Cycles	What it does	Flags
`LR A,DPCHR`	`00-03`	1	1	Load A from KU, KL, QU or QL (scratchpad 12 to 15).	none
`LR DPCHR,A`	`04-07`	1	1	Load KU, KL, QU or QL from A.	none
`LR A,r`	`40-4F`	1	1	Load A from the scratchpad register.	none
`LR r,A`	`50-5F`	1	1	Load the scratchpad register from A.	none
`LR A,IS`	`0A`	1	1	Load A from the ISAR.	none
`LR IS,A`	`0B`	1	1	Load the ISAR from A (the low six bits).	none
`LR K,P`	`08`	1	4	Load K (scratchpad 12 and 13) from the return register PC1.	none
`LR P,K`	`09`	1	4	Load the return register PC1 from K.	none
`LR Q,DC`	`0E`	1	4	Load Q (scratchpad 14 and 15) from DC0. One table read marks 0E undefined; the other sources define it.	none
`LR DC,Q`	`0F`	1	4	Load DC0 from Q.	none
`LR DC,H`	`10`	1	4	Load DC0 from H (scratchpad 10 and 11).	none
`LR H,DC`	`11`	1	4	Load H from DC0.	none
`LR W,J`	`1D`	1	2	Load the status register W from scratchpad register 9 (J).	S C Z O I
`LR J,W`	`1E`	1	1	Load scratchpad register 9 (J) from the status register W.	none
`XDC`	`2C`	1	2	Exchange DC0 and DC1.	none
`LISU`	`60-67`	1	1	Load the upper three bits of the ISAR with the value in the opcode (0 to 7).	none
`LISL`	`68-6F`	1	1	Load the lower three bits of the ISAR with the value in the opcode (0 to 7).	none
`LIS`	`70-7F`	1	1	Load A with the 4-bit value in the opcode (the upper four bits are zero). `LIS 0` is also called CLR.	none

Arithmetic, logic and shifts

Logical instructions and shifts clear C and O and set S and Z; additions set all four. Decimal addition (ASD, AMD) adds packed BCD digit pairs.

Instruction	Opcode	Bytes	Cycles	What it does	Flags
`AS`	`C0-CF`	1	1	A = A + the scratchpad register.	S C Z O
`ASD`	`D0-DF`	1	2	Decimal add: A = A + the scratchpad register as BCD.	S C Z O
`XS`	`E0-EF`	1	1	A = A XOR the scratchpad register.	S C Z O
`NS`	`F0-FF`	1	1	A = A AND the scratchpad register.	S C Z O
`DS`	`30-3F`	1	1.5	Decrement the scratchpad register (add 255); the flags describe the result. The register tested with BR7 or BNZ in a loop.	S C Z O
`INC`	`1F`	1	1	A = A + 1.	S C Z O
`LNK`	`19`	1	1	A = A + the carry flag.	S C Z O
`COM`	`18`	1	1	Complement A.	S C Z O
`SR 1`	`12`	1	1	Shift A right one bit; zero comes in at bit 7. The instruction page read lists no flags; the decoder sets S, Z and clears C, O as the core does.	S C Z O
`SL 1`	`13`	1	1	Shift A left one bit.	S C Z O
`SR 4`	`14`	1	1	Shift A right four bits.	S C Z O
`SL 4`	`15`	1	1	Shift A left four bits.	S C Z O
`ADC`	`8E`	1	2.5	DC0 = DC0 + A (A as a signed number). The page read lists flags for it inconsistently; the decoder and the core change none.	none

Immediate

Instruction	Opcode	Bytes	Cycles	What it does	Flags
`LI`	`20`	2	2.5	Load A with the immediate byte.	none
`NI`	`21`	2	2.5	A = A AND the immediate byte.	S C Z O
`OI`	`22`	2	2.5	A = A OR the immediate byte.	S C Z O
`XI`	`23`	2	2.5	A = A XOR the immediate byte.	S C Z O
`AI`	`24`	2	2.5	A = A + the immediate byte.	S C Z O
`CI`	`25`	2	2.5	Compare: the immediate byte minus A; only the flags change.	S C Z O
`DCI`	`2A`	3	6	Load DC0 with the 16-bit immediate address (high byte first).	none

Memory through DC0

These work on the byte at DC0 and increase DC0 afterwards.

Instruction	Opcode	Bytes	Cycles	What it does	Flags
`LM`	`16`	1	2.5	Load A from memory.	none
`ST`	`17`	1	2.5	Store A in memory.	none
`AM`	`88`	1	2.5	A = A + memory.	S C Z O
`AMD`	`89`	1	2.5	Decimal add memory to A (BCD).	S C Z O
`NM`	`8A`	1	2.5	A = A AND memory.	S C Z O
`OM`	`8B`	1	2.5	A = A OR memory.	S C Z O
`XM`	`8C`	1	2.5	A = A XOR memory.	S C Z O
`CM`	`8D`	1	2.5	Compare: memory minus A; only the flags change.	S C Z O

Jumps, calls and branches

JMP and PI carry an absolute address (high byte first) and leave its high byte in A. A branch has one signed displacement byte: the target is the address of the branch + 1 + the displacement, so it can reach 127 bytes forward and 128 back from the displacement byte. The cycle count is for a branch not taken and, after the slash, taken. BT and BF test the status flags with a mask; the named forms are listed with them.

Instruction	Opcode	Bytes	Cycles	What it does	Flags
`JMP`	`29`	3	5.5	Jump to the address; the high byte is left in A.	none
`PI`	`28`	3	6.5	Call: PC1 = the return address, jump to the address; the high byte is left in A.	none
`PK`	`0C`	1	4	Call the address in K: PC1 = PC0, PC0 = K.	none
`LR P0,Q`	`0D`	1	4	Jump to the address in Q (PC0 = Q).	none
`POP`	`1C`	1	2	Return: PC0 = PC1.	none
`BT`	`80-87`	2	3 / 3.5	Branch if any flag selected by the 3-bit mask is set (bit 0 S, bit 1 C, bit 2 Z): BT 1 is BP (positive), BT 2 is BC (carry), BT 4 is BZ (zero); BT 0 never branches.	none
`BF`	`90-9F`	2	3 / 3.5	Branch if none of the flags selected by the 4-bit mask (S C Z O) is set: BF 1 is BM (negative), BF 2 BNC, BF 4 BNZ, BF 8 BNO; BF 0 always branches and is called BR (3.5 cycles).	none
`BR7`	`8F`	2	3 / 3.5	Branch if the low three bits of the ISAR are not 7.	none

Input and output and control

Instruction	Opcode	Bytes	Cycles	What it does	Flags
`IN`	`26`	2	4	Input: A = the byte at the port named by the next byte (0 to 255). The instruction page read lists no flags; the decoder sets S, Z and clears C, O as the core does.	S C Z O
`OUT`	`27`	2	4	Output: A to the port named by the next byte.	none
`INS`	`A0-AF`	1	4	Input from port 0 to 15 (the low nibble) into A.	S C Z O
`OUTS`	`B0-BF`	1	4	Output A to port 0 to 15.	none
`DI`	`1A`	1	2	Disable interrupts.	I
`EI`	`1B`	1	2	Enable interrupts.	I
`NOP`	`2B`	1	1	No operation.	none

Not described

Known, not yet covered

Reference: the cycle counts in clock periods per support chip, and the interrupt entry.

Unknown

Reference: the flags of SR, SL, IN and INS and the effect of ADC on the flags (the tables read do not agree with one another or the core); the cycle counts of PK, BR7, DI, EI, LR W,J, LR J,W, INS and OUTS (the core differs from the table).

F8 Instruction Set – Instructions