Introduction
The row is the high nibble of the opcode and the column the low nibble. In the rows 3, 4, 5, C, D, E and F the low nibble is a scratchpad register designator (0 to 11, S, I, D and the undefined 15); in rows 6 and 7 it holds the value; in rows A and B the port. A cell shows the instruction. The undefined opcodes are shaded.
The map
| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x | LR A,DPCHR | LR A,DPCHR | LR A,DPCHR | LR A,DPCHR | LR DPCHR,A | LR DPCHR,A | LR DPCHR,A | LR DPCHR,A | LR K,P | LR P,K | LR A,IS | LR IS,A | PK | LR P0,Q | LR Q,DC | LR DC,Q |
| 1x | LR DC,H | LR H,DC | SR 1 | SL 1 | SR 4 | SL 4 | LM | ST | COM | LNK | DI | EI | POP | LR W,J | LR J,W | INC |
| 2x | LI | NI | OI | XI | AI | CI | IN | OUT | PI | JMP | DCI | NOP | XDC | - | - | - |
| 3x | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS | DS |
| 4x | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r | LR A,r |
| 5x | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A | LR r,A |
| 6x | LISU | LISU | LISU | LISU | LISU | LISU | LISU | LISU | LISL | LISL | LISL | LISL | LISL | LISL | LISL | LISL |
| 7x | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS | LIS |
| 8x | BT | BT | BT | BT | BT | BT | BT | BT | AM | AMD | NM | OM | XM | CM | ADC | BR7 |
| 9x | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF | BF |
| Ax | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS | INS |
| Bx | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS | OUTS |
| Cx | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS | AS |
| Dx | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD | ASD |
| Ex | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS | XS |
| Fx | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS | NS |
The undefined opcodes
Opcodes 2D, 2E and 2F have no instruction in the tables read. The explorer shows each as a one-byte DB with the status Illegal; what a real chip does is not documented in the sources read (the Channel F core read executes them as a four-clock no-operation).
Opcode 0E, which one table marks undefined, is LR Q,DC in the instruction list of the same site, in the debugger decoder and in the core.
Not described
Known, not yet covered
- Reference: the F8 variants with extra instructions (the Mostek 3870 family and later F8 parts).
Unknown
- Reference: the behaviour of 2D to 2F and of the designator 15 opcodes (marked undocumented, shaded) on real chips.
Links
Reference
- Fairchild F8 – Lee Turner’s pages